//RSP microcode

#include "../../Shared/rsp_prefix.h"
#include "../../Shared/rsp_macros.h"
#include "Microcode.h"

void _DKRData(_u32 StartAddress);

void DKR1458_1474(void);
void DKR1864_18B0(void);
void DKR1D74_1D84(void);
void DKR1D88_1E0C(void);
void DKR1E3C_1F30(void);

void _DKRBootCode(_u32 StartAddress)
{
	static _u32	JumpTable[(0x1000 >> 2)];
	static _u32	BuildJumpTable = 0;

	if (!BuildJumpTable)
	{
		BuildJumpTable = 1;
		goto _BuildJumpTable;
	}

	_Label:
	StartAddress = JumpTable[(StartAddress & 0x0FFF) >> 2];
	__asm mov eax, StartAddress
	__asm jmp eax


_04001000:	// 4001000: <34210001>	ORI       AT = AT | 0x0001
	state.r[AT] = (state.r[AT] | 0x00000001);


_04001004:	// 4001004: <0900041a>	J         04001068
	state.r[AT] = 0 + 0x0FC0;
	goto _04001068;


_04001008:	// 4001008: <20010fc0>	ADDI      AT = R0 + 0fc0
	state.r[AT] = 0 + 0x0FC0;


_0400100C:	// 400100c: <8c220010>	LW        V0 = [AT+0010]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000010) & 0xfff);


_04001010:	// 4001010: <20030f7f>	ADDI      V1 = R0 + 0f7f
	state.r[V1] = 0 + 0x0F7F;


_04001014:	// 4001014: <20071080>	ADDI      A3 = R0 + 1080
	state.r[A3] = 0 + 0x1080;


_04001018:	// 4001018: <40870000>	MTC0      SP memory address = A3
	DMEM_Address = state.r[A3];


_0400101C:	// 400101c: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_04001020:	// 4001020: <40831000>	MTC0      SP read DMA length = V1
	sp_reg_pc = 0x04001024;
	_DKRData(0x04001024);
	return;


_04001024:	// 4001024: <40043000>	MFC0      A2 = SP status
	state.r[A0] = 0;


_04001028:	// 4001028: <1480fffe>	BNE       (R0!=A0) --> 1024
	sp_reg_pc = 0x04001028;
	if (state.r[A0] != 0)
	{
		goto _04001024;
	}


_0400102C:	// 400102c: <00000000>	NOP       


_04001030:	// 4001030: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x04001030;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_04001034:	// 4001034: <00000000>	NOP       


_04001038:	// 4001038: <00e00008>	JR        A3
	{
		_u32	temp = ((state.r[A3] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_0400103C:	// 400103c: <40803800>	MTC0      SP semaphore = R0


_04001040:	// 4001040: <40082000>	MFC0      A0 = DP CMD DMA start
	state.r[T0] = 0;


_04001044:	// 4001044: <31080080>	ANDI      T0 = T0 & 0080
	state.r[T0] = (state.r[T0] & 0x00000080);


_04001048:	// 4001048: <15000002>	BNE       (R0!=T0) --> 1054
	sp_reg_pc = 0x04001048;
	if (state.r[T0] != 0)
	{
		goto _04001054;
	}


_0400104C:	// 400104c: <00000000>	NOP       


_04001050:	// 4001050: <03e00008>	JR        RA
	{
		_u32	temp = ((state.r[RA] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_04001054:	// 4001054: <40803800>	MTC0      SP semaphore = R0


_04001058:	// 4001058: <34085200>	ORI       T0 = R0 | 0x5200
	state.r[T0] = (0 | 0x00005200);


_0400105C:	// 400105c: <40882000>	MTC0      SP status = T0


_04001060:	// 4001060: <0000000d>	BREAK
	state.halt = 1;
	return;


_04001064:	// 4001064: <00000000>	NOP       


_04001068:	// 4001068: <8c220004>	LW        V0 = [AT+0004]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000004) & 0xfff);


_0400106C:	// 400106c: <30420002>	ANDI      V0 = V0 & 0002
	state.r[V0] = (state.r[V0] & 0x00000002);


_04001070:	// 4001070: <10400007>	BEQ       (R0==V0) --> 1090
	sp_reg_pc = 0x04001070;
	if (state.r[V0] == 0)
	{
		goto _04001090;
	}


_04001074:	// 4001074: <00000000>	NOP       


_04001078:	// 4001078: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x04001078;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_0400107C:	// 400107c: <00000000>	NOP       


_04001080:	// 4001080: <40025800>	MFC0      T3 = SP read DMA length
	state.r[V0] = 0;


_04001084:	// 4001084: <30420100>	ANDI      V0 = V0 & 0100
	state.r[V0] = (state.r[V0] & 0x00000100);


_04001088:	// 4001088: <1c40ffed>	BGTZ      (R0>0) --> 1040
	sp_reg_pc = 0x04001088;
	if((_s32)state.r[V0] > 0)
	{
		goto _04001040;
	}


_0400108C:	// 400108c: <00000000>	NOP       


_04001090:	// 4001090: <8c220018>	LW        V0 = [AT+0018]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000018) & 0xfff);


_04001094:	// 4001094: <8c23001c>	LW        V1 = [AT+001c]
	state.r[V1] = (_s32)Load32_DMEM((state.r[AT] + 0x0000001C) & 0xfff);


_04001098:	// 4001098: <2063ffff>	ADDI      V1 = V1 + ffff
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;


_0400109C:	// 400109c: <401e2800>	MFC0      A1 = unknown
	state.r[S8] = 0;


_040010A0:	// 40010a0: <17c0fffe>	BNE       (R0!=S8) --> 109c
	sp_reg_pc = 0x040010A0;
	if (state.r[S8] != 0)
	{
		goto _0400109C;
	}


_040010A4:	// 40010a4: <00000000>	NOP       


_040010A8:	// 40010a8: <40800000>	MTC0      SP memory address = R0
	DMEM_Address = 0;


_040010AC:	// 40010ac: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_040010B0:	// 40010b0: <40831000>	MTC0      SP read DMA length = V1
	sp_reg_pc = 0x040010B0;
	DMARead(state.r[V1]);


_040010B4:	// 40010b4: <40043000>	MFC0      A2 = SP status
	state.r[A0] = 0;


_040010B8:	// 40010b8: <1480fffe>	BNE       (R0!=A0) --> 10b4
	sp_reg_pc = 0x040010B8;
	if (state.r[A0] != 0)
	{
		goto _040010B4;
	}


_040010BC:	// 40010bc: <00000000>	NOP       


_040010C0:	// 40010c0: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x040010C0;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_040010C4:	// 40010c4: <00000000>	NOP       


_040010C8:	// 40010c8: <09000403>	J         0400100c
	goto _0400100C;


_040010CC:	// 40010cc: <00000000>	NOP       

_040010D0:
_040010D4:
_040010D8:
_040010DC:
_040010E0:
_040010E4:
_040010E8:
_040010EC:
_040010F0:
_040010F4:
_040010F8:
_040010FC:
_04001100:
_04001104:
_04001108:
_0400110C:
_04001110:
_04001114:
_04001118:
_0400111C:
_04001120:
_04001124:
_04001128:
_0400112C:
_04001130:
_04001134:
_04001138:
_0400113C:
_04001140:
_04001144:
_04001148:
_0400114C:
_04001150:
_04001154:
_04001158:
_0400115C:
_04001160:
_04001164:
_04001168:
_0400116C:
_04001170:
_04001174:
_04001178:
_0400117C:
_04001180:
_04001184:
_04001188:
_0400118C:
_04001190:
_04001194:
_04001198:
_0400119C:
_040011A0:
_040011A4:
_040011A8:
_040011AC:
_040011B0:
_040011B4:
_040011B8:
_040011BC:
_040011C0:
_040011C4:
_040011C8:
_040011CC:
_040011D0:
_040011D4:
_040011D8:
_040011DC:
_040011E0:
_040011E4:
_040011E8:
_040011EC:
_040011F0:
_040011F4:
_040011F8:
_040011FC:
_04001200:
_04001204:
_04001208:
_0400120C:
_04001210:
_04001214:
_04001218:
_0400121C:
_04001220:
_04001224:
_04001228:
_0400122C:
_04001230:
_04001234:
_04001238:
_0400123C:
_04001240:
_04001244:
_04001248:
_0400124C:
_04001250:
_04001254:
_04001258:
_0400125C:
_04001260:
_04001264:
_04001268:
_0400126C:
_04001270:
_04001274:
_04001278:
_0400127C:
_04001280:
_04001284:
_04001288:
_0400128C:
_04001290:
_04001294:
_04001298:
_0400129C:
_040012A0:
_040012A4:
_040012A8:
_040012AC:
_040012B0:
_040012B4:
_040012B8:
_040012BC:
_040012C0:
_040012C4:
_040012C8:
_040012CC:
_040012D0:
_040012D4:
_040012D8:
_040012DC:
_040012E0:
_040012E4:
_040012E8:
_040012EC:
_040012F0:
_040012F4:
_040012F8:
_040012FC:
_04001300:
_04001304:
_04001308:
_0400130C:
_04001310:
_04001314:
_04001318:
_0400131C:
_04001320:
_04001324:
_04001328:
_0400132C:
_04001330:
_04001334:
_04001338:
_0400133C:
_04001340:
_04001344:
_04001348:
_0400134C:
_04001350:
_04001354:
_04001358:
_0400135C:
_04001360:
_04001364:
_04001368:
_0400136C:
_04001370:
_04001374:
_04001378:
_0400137C:
_04001380:
_04001384:
_04001388:
_0400138C:
_04001390:
_04001394:
_04001398:
_0400139C:
_040013A0:
_040013A4:
_040013A8:
_040013AC:
_040013B0:
_040013B4:
_040013B8:
_040013BC:
_040013C0:
_040013C4:
_040013C8:
_040013CC:
_040013D0:
_040013D4:
_040013D8:
_040013DC:
_040013E0:
_040013E4:
_040013E8:
_040013EC:
_040013F0:
_040013F4:
_040013F8:
_040013FC:
_04001400:
_04001404:
_04001408:
_0400140C:
_04001410:
_04001414:
_04001418:
_0400141C:
_04001420:
_04001424:
_04001428:
_0400142C:
_04001430:
_04001434:
_04001438:
_0400143C:
_04001440:
_04001444:
_04001448:
_0400144C:
_04001450:
_04001454:
_04001458:
_0400145C:
_04001460:
_04001464:
_04001468:
_0400146C:
_04001470:
_04001474:
_04001478:
_0400147C:
_04001480:
_04001484:
_04001488:
_0400148C:
_04001490:
_04001494:
_04001498:
_0400149C:
_040014A0:
_040014A4:
_040014A8:
_040014AC:
_040014B0:
_040014B4:
_040014B8:
_040014BC:
_040014C0:
_040014C4:
_040014C8:
_040014CC:
_040014D0:
_040014D4:
_040014D8:
_040014DC:
_040014E0:
_040014E4:
_040014E8:
_040014EC:
_040014F0:
_040014F4:
_040014F8:
_040014FC:
_04001500:
_04001504:
_04001508:
_0400150C:
_04001510:
_04001514:
_04001518:
_0400151C:
_04001520:
_04001524:
_04001528:
_0400152C:
_04001530:
_04001534:
_04001538:
_0400153C:
_04001540:
_04001544:
_04001548:
_0400154C:
_04001550:
_04001554:
_04001558:
_0400155C:
_04001560:
_04001564:
_04001568:
_0400156C:
_04001570:
_04001574:
_04001578:
_0400157C:
_04001580:
_04001584:
_04001588:
_0400158C:
_04001590:
_04001594:
_04001598:
_0400159C:
_040015A0:
_040015A4:
_040015A8:
_040015AC:
_040015B0:
_040015B4:
_040015B8:
_040015BC:
_040015C0:
_040015C4:
_040015C8:
_040015CC:
_040015D0:
_040015D4:
_040015D8:
_040015DC:
_040015E0:
_040015E4:
_040015E8:
_040015EC:
_040015F0:
_040015F4:
_040015F8:
_040015FC:
_04001600:
_04001604:
_04001608:
_0400160C:
_04001610:
_04001614:
_04001618:
_0400161C:
_04001620:
_04001624:
_04001628:
_0400162C:
_04001630:
_04001634:
_04001638:
_0400163C:
_04001640:
_04001644:
_04001648:
_0400164C:
_04001650:
_04001654:
_04001658:
_0400165C:
_04001660:
_04001664:
_04001668:
_0400166C:
_04001670:
_04001674:
_04001678:
_0400167C:
_04001680:
_04001684:
_04001688:
_0400168C:
_04001690:
_04001694:
_04001698:
_0400169C:
_040016A0:
_040016A4:
_040016A8:
_040016AC:
_040016B0:
_040016B4:
_040016B8:
_040016BC:
_040016C0:
_040016C4:
_040016C8:
_040016CC:
_040016D0:
_040016D4:
_040016D8:
_040016DC:
_040016E0:
_040016E4:
_040016E8:
_040016EC:
_040016F0:
_040016F4:
_040016F8:
_040016FC:
_04001700:
_04001704:
_04001708:
_0400170C:
_04001710:
_04001714:
_04001718:
_0400171C:
_04001720:
_04001724:
_04001728:
_0400172C:
_04001730:
_04001734:
_04001738:
_0400173C:
_04001740:
_04001744:
_04001748:
_0400174C:
_04001750:
_04001754:
_04001758:
_0400175C:
_04001760:
_04001764:
_04001768:
_0400176C:
_04001770:
_04001774:
_04001778:
_0400177C:
_04001780:
_04001784:
_04001788:
_0400178C:
_04001790:
_04001794:
_04001798:
_0400179C:
_040017A0:
_040017A4:
_040017A8:
_040017AC:
_040017B0:
_040017B4:
_040017B8:
_040017BC:
_040017C0:
_040017C4:
_040017C8:
_040017CC:
_040017D0:
_040017D4:
_040017D8:
_040017DC:
_040017E0:
_040017E4:
_040017E8:
_040017EC:
_040017F0:
_040017F4:
_040017F8:
_040017FC:
_04001800:
_04001804:
_04001808:
_0400180C:
_04001810:
_04001814:
_04001818:
_0400181C:
_04001820:
_04001824:
_04001828:
_0400182C:
_04001830:
_04001834:
_04001838:
_0400183C:
_04001840:
_04001844:
_04001848:
_0400184C:
_04001850:
_04001854:
_04001858:
_0400185C:
_04001860:
_04001864:
_04001868:
_0400186C:
_04001870:
_04001874:
_04001878:
_0400187C:
_04001880:
_04001884:
_04001888:
_0400188C:
_04001890:
_04001894:
_04001898:
_0400189C:
_040018A0:
_040018A4:
_040018A8:
_040018AC:
_040018B0:
_040018B4:
_040018B8:
_040018BC:
_040018C0:
_040018C4:
_040018C8:
_040018CC:
_040018D0:
_040018D4:
_040018D8:
_040018DC:
_040018E0:
_040018E4:
_040018E8:
_040018EC:
_040018F0:
_040018F4:
_040018F8:
_040018FC:
_04001900:
_04001904:
_04001908:
_0400190C:
_04001910:
_04001914:
_04001918:
_0400191C:
_04001920:
_04001924:
_04001928:
_0400192C:
_04001930:
_04001934:
_04001938:
_0400193C:
_04001940:
_04001944:
_04001948:
_0400194C:
_04001950:
_04001954:
_04001958:
_0400195C:
_04001960:
_04001964:
_04001968:
_0400196C:
_04001970:
_04001974:
_04001978:
_0400197C:
_04001980:
_04001984:
_04001988:
_0400198C:
_04001990:
_04001994:
_04001998:
_0400199C:
_040019A0:
_040019A4:
_040019A8:
_040019AC:
_040019B0:
_040019B4:
_040019B8:
_040019BC:
_040019C0:
_040019C4:
_040019C8:
_040019CC:
_040019D0:
_040019D4:
_040019D8:
_040019DC:
_040019E0:
_040019E4:
_040019E8:
_040019EC:
_040019F0:
_040019F4:
_040019F8:
_040019FC:
_04001A00:
_04001A04:
_04001A08:
_04001A0C:
_04001A10:
_04001A14:
_04001A18:
_04001A1C:
_04001A20:
_04001A24:
_04001A28:
_04001A2C:
_04001A30:
_04001A34:
_04001A38:
_04001A3C:
_04001A40:
_04001A44:
_04001A48:
_04001A4C:
_04001A50:
_04001A54:
_04001A58:
_04001A5C:
_04001A60:
_04001A64:
_04001A68:
_04001A6C:
_04001A70:
_04001A74:
_04001A78:
_04001A7C:
_04001A80:
_04001A84:
_04001A88:
_04001A8C:
_04001A90:
_04001A94:
_04001A98:
_04001A9C:
_04001AA0:
_04001AA4:
_04001AA8:
_04001AAC:
_04001AB0:
_04001AB4:
_04001AB8:
_04001ABC:
_04001AC0:
_04001AC4:
_04001AC8:
_04001ACC:
_04001AD0:
_04001AD4:
_04001AD8:
_04001ADC:
_04001AE0:
_04001AE4:
_04001AE8:
_04001AEC:
_04001AF0:
_04001AF4:
_04001AF8:
_04001AFC:
_04001B00:
_04001B04:
_04001B08:
_04001B0C:
_04001B10:
_04001B14:
_04001B18:
_04001B1C:
_04001B20:
_04001B24:
_04001B28:
_04001B2C:
_04001B30:
_04001B34:
_04001B38:
_04001B3C:
_04001B40:
_04001B44:
_04001B48:
_04001B4C:
_04001B50:
_04001B54:
_04001B58:
_04001B5C:
_04001B60:
_04001B64:
_04001B68:
_04001B6C:
_04001B70:
_04001B74:
_04001B78:
_04001B7C:
_04001B80:
_04001B84:
_04001B88:
_04001B8C:
_04001B90:
_04001B94:
_04001B98:
_04001B9C:
_04001BA0:
_04001BA4:
_04001BA8:
_04001BAC:
_04001BB0:
_04001BB4:
_04001BB8:
_04001BBC:
_04001BC0:
_04001BC4:
_04001BC8:
_04001BCC:
_04001BD0:
_04001BD4:
_04001BD8:
_04001BDC:
_04001BE0:
_04001BE4:
_04001BE8:
_04001BEC:
_04001BF0:
_04001BF4:
_04001BF8:
_04001BFC:
_04001C00:
_04001C04:
_04001C08:
_04001C0C:
_04001C10:
_04001C14:
_04001C18:
_04001C1C:
_04001C20:
_04001C24:
_04001C28:
_04001C2C:
_04001C30:
_04001C34:
_04001C38:
_04001C3C:
_04001C40:
_04001C44:
_04001C48:
_04001C4C:
_04001C50:
_04001C54:
_04001C58:
_04001C5C:
_04001C60:
_04001C64:
_04001C68:
_04001C6C:
_04001C70:
_04001C74:
_04001C78:
_04001C7C:
_04001C80:
_04001C84:
_04001C88:
_04001C8C:
_04001C90:
_04001C94:
_04001C98:
_04001C9C:
_04001CA0:
_04001CA4:
_04001CA8:
_04001CAC:
_04001CB0:
_04001CB4:
_04001CB8:
_04001CBC:
_04001CC0:
_04001CC4:
_04001CC8:
_04001CCC:
_04001CD0:
_04001CD4:
_04001CD8:
_04001CDC:
_04001CE0:
_04001CE4:
_04001CE8:
_04001CEC:
_04001CF0:
_04001CF4:
_04001CF8:
_04001CFC:
_04001D00:
_04001D04:
_04001D08:
_04001D0C:
_04001D10:
_04001D14:
_04001D18:
_04001D1C:
_04001D20:
_04001D24:
_04001D28:
_04001D2C:
_04001D30:
_04001D34:
_04001D38:
_04001D3C:
_04001D40:
_04001D44:
_04001D48:
_04001D4C:
_04001D50:
_04001D54:
_04001D58:
_04001D5C:
_04001D60:
_04001D64:
_04001D68:
_04001D6C:
_04001D70:
_04001D74:
_04001D78:
_04001D7C:
_04001D80:
_04001D84:
_04001D88:
_04001D8C:
_04001D90:
_04001D94:
_04001D98:
_04001D9C:
_04001DA0:
_04001DA4:
_04001DA8:
_04001DAC:
_04001DB0:
_04001DB4:
_04001DB8:
_04001DBC:
_04001DC0:
_04001DC4:
_04001DC8:
_04001DCC:
_04001DD0:
_04001DD4:
_04001DD8:
_04001DDC:
_04001DE0:
_04001DE4:
_04001DE8:
_04001DEC:
_04001DF0:
_04001DF4:
_04001DF8:
_04001DFC:
_04001E00:
_04001E04:
_04001E08:
_04001E0C:
_04001E10:
_04001E14:
_04001E18:
_04001E1C:
_04001E20:
_04001E24:
_04001E28:
_04001E2C:
_04001E30:
_04001E34:
_04001E38:
_04001E3C:
_04001E40:
_04001E44:
_04001E48:
_04001E4C:
_04001E50:
_04001E54:
_04001E58:
_04001E5C:
_04001E60:
_04001E64:
_04001E68:
_04001E6C:
_04001E70:
_04001E74:
_04001E78:
_04001E7C:
_04001E80:
_04001E84:
_04001E88:
_04001E8C:
_04001E90:
_04001E94:
_04001E98:
_04001E9C:
_04001EA0:
_04001EA4:
_04001EA8:
_04001EAC:
_04001EB0:
_04001EB4:
_04001EB8:
_04001EBC:
_04001EC0:
_04001EC4:
_04001EC8:
_04001ECC:
_04001ED0:
_04001ED4:
_04001ED8:
_04001EDC:
_04001EE0:
_04001EE4:
_04001EE8:
_04001EEC:
_04001EF0:
_04001EF4:
_04001EF8:
_04001EFC:
_04001F00:
_04001F04:
_04001F08:
_04001F0C:
_04001F10:
_04001F14:
_04001F18:
_04001F1C:
_04001F20:
_04001F24:
_04001F28:
_04001F2C:
_04001F30:
_04001F34:
_04001F38:
_04001F3C:
_04001F40:
_04001F44:
_04001F48:
_04001F4C:
_04001F50:
_04001F54:
_04001F58:
_04001F5C:
_04001F60:
_04001F64:
_04001F68:
_04001F6C:
_04001F70:
_04001F74:
_04001F78:
_04001F7C:
_04001F80:
_04001F84:
_04001F88:
_04001F8C:
_04001F90:
_04001F94:
_04001F98:
_04001F9C:
_04001FA0:
_04001FA4:
_04001FA8:
_04001FAC:
_04001FB0:
_04001FB4:
_04001FB8:
_04001FBC:
_04001FC0:
_04001FC4:
_04001FC8:
_04001FCC:
_04001FD0:
_04001FD4:
_04001FD8:
_04001FDC:
_04001FE0:
_04001FE4:
_04001FE8:
_04001FEC:
_04001FF0:
_04001FF4:
_04001FF8:
_04001FFC:
	state.halt = 1;
	return;

	_BuildJumpTable:
	#include "jumptable.h"
	goto _Label;
}

void _DKRData(_u32 StartAddress)
{
	static _u32	JumpTable[(0x1000 >> 2)];
	static _u32	BuildJumpTable = 0;

	if (!BuildJumpTable)
	{
		BuildJumpTable = 1;
		goto _BuildJumpTable;
	}

	_Label:
	StartAddress = JumpTable[(StartAddress & 0x0FFF) >> 2];
	__asm mov eax, StartAddress
	__asm jmp eax


_04001000:	// 4001000: <34210001>	ORI       AT = AT | 0x0001
	state.r[AT] = (state.r[AT] | 0x00000001);


_04001004:	// 4001004: <0900041a>	J         04001068
	state.r[AT] = 0 + 0x0FC0;
	goto _04001068;


_04001008:	// 4001008: <20010fc0>	ADDI      AT = R0 + 0fc0
	state.r[AT] = 0 + 0x0FC0;


_0400100C:	// 400100c: <8c220010>	LW        V0 = [AT+0010]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000010) & 0xfff);


_04001010:	// 4001010: <20030f7f>	ADDI      V1 = R0 + 0f7f
	state.r[V1] = 0 + 0x0F7F;


_04001014:	// 4001014: <20071080>	ADDI      A3 = R0 + 1080
	state.r[A3] = 0 + 0x1080;


_04001018:	// 4001018: <40870000>	MTC0      SP memory address = A3
	DMEM_Address = state.r[A3];


_0400101C:	// 400101c: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_04001020:	// 4001020: <40831000>	MTC0      SP read DMA length = V1
	sp_reg_pc = 0x04001024;
	_DKRData(0x04001024);
	return;


_04001024:	// 4001024: <40043000>	MFC0      A2 = SP status
	state.r[A0] = 0;


_04001028:	// 4001028: <1480fffe>	BNE       (R0!=A0) --> 1024
	sp_reg_pc = 0x04001028;
	if (state.r[A0] != 0)
	{
		goto _04001024;
	}


_0400102C:	// 400102c: <00000000>	NOP       


_04001030:	// 4001030: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x04001030;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_04001034:	// 4001034: <00000000>	NOP       


_04001038:	// 4001038: <00e00008>	JR        A3
	{
		_u32	temp = ((state.r[A3] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_0400103C:	// 400103c: <40803800>	MTC0      SP semaphore = R0


_04001040:	// 4001040: <40082000>	MFC0      A0 = DP CMD DMA start
	state.r[T0] = 0;


_04001044:	// 4001044: <31080080>	ANDI      T0 = T0 & 0080
	state.r[T0] = (state.r[T0] & 0x00000080);


_04001048:	// 4001048: <15000002>	BNE       (R0!=T0) --> 1054
	sp_reg_pc = 0x04001048;
	if (state.r[T0] != 0)
	{
		goto _04001054;
	}


_0400104C:	// 400104c: <00000000>	NOP       


_04001050:	// 4001050: <03e00008>	JR        RA
	{
		_u32	temp = ((state.r[RA] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_04001054:	// 4001054: <40803800>	MTC0      SP semaphore = R0


_04001058:	// 4001058: <34085200>	ORI       T0 = R0 | 0x5200
	state.r[T0] = (0 | 0x00005200);


_0400105C:	// 400105c: <40882000>	MTC0      SP status = T0


_04001060:	// 4001060: <0000000d>	BREAK
	state.halt = 1;
	return;


_04001064:	// 4001064: <00000000>	NOP       


_04001068:	// 4001068: <8c220004>	LW        V0 = [AT+0004]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000004) & 0xfff);


_0400106C:	// 400106c: <30420002>	ANDI      V0 = V0 & 0002
	state.r[V0] = (state.r[V0] & 0x00000002);


_04001070:	// 4001070: <10400007>	BEQ       (R0==V0) --> 1090
	sp_reg_pc = 0x04001070;
	if (state.r[V0] == 0)
	{
		goto _04001090;
	}


_04001074:	// 4001074: <00000000>	NOP       


_04001078:	// 4001078: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x04001078;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_0400107C:	// 400107c: <00000000>	NOP       


_04001080:	// 4001080: <20180360>	ADDI      T8 = R0 + 0360
	state.r[T8] = 0 + 0x0360;


_04001084:	// 4001084: <20170f90>	ADDI      S7 = R0 + 0f90
	state.r[S7] = 0 + 0x0F90;


_04001088:	// 4001088: <8c3c0030>	LW        GP = [AT+0030]
	state.r[GP] = (_s32)Load32_DMEM((state.r[AT] + 0x00000030) & 0xfff);


_0400108C:	// 400108c: <8c3b0034>	LW        K1 = [AT+0034]
	state.r[K1] = (_s32)Load32_DMEM((state.r[AT] + 0x00000034) & 0xfff);


_04001090:	// 4001090: <40055800>	MFC0      T3 = SP DMA full
	state.r[A1] = 0;


_04001094:	// 4001094: <30a40001>	ANDI      A0 = A1 & 0001
	state.r[A0] = (state.r[A1] & 0x00000001);


_04001098:	// 4001098: <10800006>	BEQ       (R0==A0) --> 10b4
	sp_reg_pc = 0x04001098;
	if (state.r[A0] == 0)
	{
		state.r[A0] = (state.r[A1] & 0x00000100);
		goto _040010B4;
	}


_0400109C:	// 400109c: <30a40100>	ANDI      A0 = A1 & 0100
	state.r[A0] = (state.r[A1] & 0x00000100);


_040010A0:	// 40010a0: <10800004>	BEQ       (R0==A0) --> 10b4
	sp_reg_pc = 0x040010A0;
	if (state.r[A0] == 0)
	{
		goto _040010B4;
	}


_040010A4:	// 40010a4: <00000000>	NOP       


_040010A8:	// 40010a8: <40045800>	MFC0      T3 = SP status
	state.r[A0] = 0;


_040010AC:	// 40010ac: <30840100>	ANDI      A0 = A0 & 0100
	state.r[A0] = (state.r[A0] & 0x00000100);


_040010B0:	// 40010b0: <1c80fffd>	BGTZ      (R0>0) --> 10a8
	sp_reg_pc = 0x040010B0;
	if((_s32)state.r[A0] > 0)
	{
		goto _040010A8;
	}


_040010B4:	// 40010b4: <00000000>	NOP       


_040010B8:	// 40010b8: <0d000458>	JAL	    04001160
	sp_reg_pc = 0x040010B8;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001160;


_040010BC:	// 40010bc: <00000000>	NOP       


_040010C0:	// 40010c0: <2002000f>	ADDI      V0 = R0 + 000f
	state.r[V0] = 0 + 0x000F;


_040010C4:	// 40010c4: <20010320>	ADDI      AT = R0 + 0320
	state.r[AT] = 0 + 0x0320;


_040010C8:	// 40010c8: <ac200000>	SW        [AT+0000] = R0
	Save32_DMEM((_u32)0, (state.r[AT] + 0x00000000) & 0xfff);


_040010CC:	// 40010cc: <1c40fffe>	BGTZ      (R0>0) --> 10c8
	sp_reg_pc = 0x040010CC;
	if((_s32)state.r[V0] > 0)
	{
		state.r[V0] = state.r[V0] + 0xFFFFFFFF;
		goto _040010C8;
	}


_040010D0:	// 40010d0: <2042ffff>	ADDI      V0 = V0 + ffff
	state.r[V0] = state.r[V0] + 0xFFFFFFFF;


_040010D4:	// 40010d4: <40023000>	MFC0      A2 = SP read DMA length
	state.r[V0] = 0;


_040010D8:	// 40010d8: <1440fffe>	BNE       (R0!=V0) --> 10d4
	sp_reg_pc = 0x040010D8;
	if (state.r[V0] != 0)
	{
		state.r[SP] = 0 + 0x0380;
		goto _040010D4;
	}


_040010DC:	// 40010dc: <201d0380>	ADDI      SP = R0 + 0380
	state.r[SP] = 0 + 0x0380;


_040010E0:	// 40010e0: <40803800>	MTC0      SP semaphore = R0


_040010E4:	// 40010e4: <8fba0000>	LW        K0 = [SP+0000]
	// In function: Main_Parser
	//Call the function: Main_Parser
	Main_Parser();
	goto _0400110C;

_040010E8:	// 40010e8: <8fb90004>	LW        T9 = [SP+0004]
	ErrorToCallFunction(0x040010E8);

_040010EC:	// 40010ec: <001a0dc2>	SRL       AT = K0 >> 23
	ErrorToCallFunction(0x040010EC);

_040010F0:	// 40010f0: <302100fe>	ANDI      AT = AT & 00fe
	ErrorToCallFunction(0x040010F0);

_040010F4:	// 40010f4: <239c0008>	ADDI      GP = GP + 0008
	ErrorToCallFunction(0x040010F4);

_040010F8:	// 40010f8: <237bfff8>	ADDI      K1 = K1 + fff8
	ErrorToCallFunction(0x040010F8);

_040010FC:	// 40010fc: <23bd0008>	ADDI      SP = SP + 0008
	ErrorToCallFunction(0x040010FC);

_04001100:	// 4001100: <23defff8>	ADDI      S8 = S8 + fff8
	ErrorToCallFunction(0x04001100);

_04001104:	// 4001104: <00011020>	ADD       V0 = R0+AT
	ErrorToCallFunction(0x04001104);

_04001108:	// 4001108: <84420010>	LH        V0 = [V0+0010]
	ErrorToCallFunction(0x04001108);

_0400110C:	// 400110c: <00400008>	JR        V0
	{
		_u32	temp = ((state.r[V0] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_04001110:	// 4001110: <00000000>	NOP       


_04001114:	// 4001114: <0000000d>	BREAK
	state.halt = 1;
	return;


_04001118:	// 4001118: <1fc0fff2>	BGTZ      (R0>0) --> 10e4
	sp_reg_pc = 0x04001118;
	if((_s32)state.r[S8] > 0)
	{
		goto _040010E4;
	}


_0400111C:	// 400111c: <00000000>	NOP       


_04001120:	// 4001120: <1b600005>	BLEZ      (R0<=0) --> 1138
	sp_reg_pc = 0x04001120;
	if ((_s32)state.r[K1] <= 0)
	{
		goto _04001138;
	}


_04001124:	// 4001124: <00000000>	NOP       


_04001128:	// 4001128: <0d000458>	JAL	    04001160
	sp_reg_pc = 0x04001128;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001160;


_0400112C:	// 400112c: <00000000>	NOP       


_04001130:	// 4001130: <09000435>	J         040010d4
	goto _040010D4;


_04001134:	// 4001134: <00000000>	NOP       


_04001138:	// 4001138: <40013000>	MFC0      A2 = SP DRAM DMA address
	state.r[AT] = 0;


_0400113C:	// 400113c: <1420fffe>	BNE       (R0!=AT) --> 1138
	sp_reg_pc = 0x0400113C;
	if (state.r[AT] != 0)
	{
		goto _04001138;
	}


_04001140:	// 4001140: <00000000>	NOP       


_04001144:	// 4001144: <40803800>	MTC0      SP semaphore = R0


_04001148:	// 4001148: <34014000>	ORI       AT = R0 | 0x4000
	state.r[AT] = (0 | 0x00004000);


_0400114C:	// 400114c: <40812000>	MTC0      SP status = AT


_04001150:	// 4001150: <0000000d>	BREAK
	state.halt = 1;
	return;


_04001154:	// 4001154: <00000000>	NOP       


_04001158:	// 4001158: <1000ffff>	BEQ       (R0==R0) --> 1158
	sp_reg_pc = 0x04001158;
	if (0 == 0)
	{
		goto _04001158;
	}


_0400115C:	// 400115c: <00000000>	NOP       


_04001160:	// 4001160: <23e50000>	ADDI      A1 = RA + 0000
	state.r[A1] = state.r[RA] + 0x0000;


_04001164:	// 4001164: <001c1020>	ADD       V0 = R0+GP
	state.r[V0] = (0 + state.r[GP]);


_04001168:	// 4001168: <23630000>	ADDI      V1 = K1 + 0000
	state.r[V1] = state.r[K1] + 0x0000;


_0400116C:	// 400116c: <2064fec0>	ADDI      A0 = V1 + fec0
	state.r[A0] = state.r[V1] + 0xFFFFFEC0;


_04001170:	// 4001170: <18800002>	BLEZ      (R0<=0) --> 117c
	sp_reg_pc = 0x04001170;
	if ((_s32)state.r[A0] <= 0)
	{
		state.r[AT] = 0 + 0x0380;
		goto _0400117C;
	}


_04001174:	// 4001174: <20010380>	ADDI      AT = R0 + 0380
	state.r[AT] = 0 + 0x0380;


_04001178:	// 4001178: <20030140>	ADDI      V1 = R0 + 0140
	state.r[V1] = 0 + 0x0140;


_0400117C:	// 400117c: <207e0000>	ADDI      S8 = V1 + 0000
	state.r[S8] = state.r[V1] + 0x0000;


_04001180:	// 4001180: <0d000465>	JAL	    04001194
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;
	sp_reg_pc = 0x04001180;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_04001184:	// 4001184: <2063ffff>	ADDI      V1 = V1 + ffff
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;


_04001188:	// 4001188: <201d0380>	ADDI      SP = R0 + 0380
	state.r[SP] = 0 + 0x0380;


_0400118C:	// 400118c: <00a00008>	JR        A1
	{
		_u32	temp = ((state.r[A1] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_04001190:	// 4001190: <00000000>	NOP       


_04001194:	// 4001194: <40043800>	MFC0      A3 = SP status
	state.r[A0] = 0;


_04001198:	// 4001198: <40042800>	MFC0      A1 = SP status
	state.r[A0] = 0;


_0400119C:	// 400119c: <1480fffe>	BNE       (R0!=A0) --> 1198
	sp_reg_pc = 0x0400119C;
	if (state.r[A0] != 0)
	{
		goto _04001198;
	}


_040011A0:	// 40011a0: <00000000>	NOP       


_040011A4:	// 40011a4: <40810000>	MTC0      SP memory address = AT
	DMEM_Address = state.r[AT];


_040011A8:	// 40011a8: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_040011AC:	// 40011ac: <40831000>	MTC0      SP read DMA length = V1
	sp_reg_pc = 0x040011AC;
	DMARead(state.r[V1]);


_040011B0:	// 40011b0: <3c048000>	LUI       A0 = 0x80000000
	state.r[A0] = 0x80000000;


_040011B4:	// 40011b4: <0096b025>	OR        S6 = A0 | S6
	state.r[S6] = (state.r[A0] | state.r[S6]);


_040011B8:	// 40011b8: <03e00008>	JR        RA
	{
		_u32	temp = ((state.r[RA] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_040011BC:	// 40011bc: <00000000>	NOP       


_040011C0:	// 40011c0: <40043800>	MFC0      A3 = SP status
	state.r[A0] = 0;


_040011C4:	// 40011c4: <40042800>	MFC0      A1 = SP status
	state.r[A0] = 0;


_040011C8:	// 40011c8: <1480fffe>	BNE       (R0!=A0) --> 11c4
	sp_reg_pc = 0x040011C8;
	if (state.r[A0] != 0)
	{
		goto _040011C4;
	}


_040011CC:	// 40011cc: <00000000>	NOP       


_040011D0:	// 40011d0: <40810000>	MTC0      SP memory address = AT
	DMEM_Address = state.r[AT];


_040011D4:	// 40011d4: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_040011D8:	// 40011d8: <40831800>	MTC0      SP write DMA length = V1
	DMAWrite(state.r[V1]);


_040011DC:	// 40011dc: <3c048000>	LUI       A0 = 0x80000000
	state.r[A0] = 0x80000000;


_040011E0:	// 40011e0: <0096b025>	OR        S6 = A0 | S6
	state.r[S6] = (state.r[A0] | state.r[S6]);


_040011E4:	// 40011e4: <03e00008>	JR        RA
	{
		_u32	temp = ((state.r[RA] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_040011E8:	// 40011e8: <00000000>	NOP       


_040011EC:	// 40011ec: <3323ffff>	ANDI      V1 = T9 & ffff
	state.r[V1] = (state.r[T9] & 0x0000FFFF);


_040011F0:	// 40011f0: <1060ffc9>	BEQ       (R0==V1) --> 1118
	sp_reg_pc = 0x040011F0;
	if (state.r[V1] == 0)
	{
		state.r[A0] = 0 + 0x05C0;
		goto _04001118;
	}


_040011F4:	// 40011f4: <200405c0>	ADDI      A0 = R0 + 05c0
	state.r[A0] = 0 + 0x05C0;


_040011F8:	// 40011f8: <3341ffff>	ANDI      AT = K0 & ffff
	state.r[AT] = (state.r[K0] & 0x0000FFFF);


_040011FC:	// 40011fc: <00240820>	ADD       AT = AT+A0
	state.r[AT] = (state.r[AT] + state.r[A0]);


_04001200:	// 4001200: <4a01086c>	VXOR      vec01 = vec01 xor vec01[<none>]
	rsp_cop2_vxor(&state.v[1], &state.v[1], &state.v[1]);


_04001204:	// 4001204: <2063fff0>	ADDI      V1 = V1 + fff0
	state.r[V1] = state.r[V1] + 0xFFFFFFF0;


_04001208:	// 4001208: <12c00005>	BEQ       (R0==S6) --> 1220
	sp_reg_pc = 0x04001208;
	if (state.r[S6] == 0)
	{
		goto _04001220;
	}


_0400120C:	// 400120c: <00000000>	NOP       


_04001210:	// 4001210: <40053000>	MFC0      A2 = SP DMA full
	state.r[A1] = 0;


_04001214:	// 4001214: <14a0fffe>	BNE       (R0!=A1) --> 1210
	sp_reg_pc = 0x04001214;
	if (state.r[A1] != 0)
	{
		goto _04001210;
	}


_04001218:	// 4001218: <00000000>	NOP       


_0400121C:	// 400121c: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_04001220:	// 4001220: <e8211800>	SDV       [AT + 0x00] = vec01 <00>
	{
		_u32	addr = (0x00000000 + state.r[AT]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[1].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[1].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[1].U32[0x00000003];
		}
	}


_04001224:	// 4001224: <e8211801>	SDV       [AT + 0x04] = vec01 <00>
	{
		_u32	addr = (0x00000008 + state.r[AT]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[1].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[1].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[1].U32[0x00000003];
		}
	}


_04001228:	// 4001228: <20210010>	ADDI      AT = AT + 0010
	state.r[AT] = state.r[AT] + 0x0010;


_0400122C:	// 400122c: <1c60fffc>	BGTZ      (R0>0) --> 1220
	sp_reg_pc = 0x0400122C;
	if((_s32)state.r[V1] > 0)
	{
		state.r[V1] = state.r[V1] + 0xFFFFFFF0;
		goto _04001220;
	}


_04001230:	// 4001230: <2063fff0>	ADDI      V1 = V1 + fff0
	state.r[V1] = state.r[V1] + 0xFFFFFFF0;


_04001234:	// 4001234: <09000446>	J         04001118
	goto _04001118;


_04001238:	// 4001238: <00000000>	NOP       


_0400123C:	// 400123c: <97030004>	LHU       V1 = [T8+0004]
	state.r[V1] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_04001240:	// 4001240: <1060ffb5>	BEQ       (R0==V1) --> 1118
	sp_reg_pc = 0x04001240;
	if (state.r[V1] == 0)
	{
		state.r[V0] = ((_u32)state.r[T9] << 8);
		goto _04001118;
	}


_04001244:	// 4001244: <00191200>	SLL       V0 = T9 << 8
	state.r[V0] = ((_u32)state.r[T9] << 8);


_04001248:	// 4001248: <00021202>	SRL       V0 = V0 >> 8
	state.r[V0] = ((_u32)state.r[V0] >> 8);


_0400124C:	// 400124c: <00192602>	SRL       A0 = T9 >> 24
	state.r[A0] = ((_u32)state.r[T9] >> 24);


_04001250:	// 4001250: <00042080>	SLL       A0 = A0 << 2
	state.r[A0] = ((_u32)state.r[A0] << 2);


_04001254:	// 4001254: <8c850320>	LW        A1 = [A0+0320]
	state.r[A1] = (_s32)Load32_DMEM((state.r[A0] + 0x00000320) & 0xfff);


_04001258:	// 4001258: <00451020>	ADD       V0 = V0+A1
	state.r[V0] = (state.r[V0] + state.r[A1]);


_0400125C:	// 400125c: <97010000>	LHU       AT = [T8+0000]
	state.r[AT] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000000) & 0xfff);


_04001260:	// 4001260: <0d000465>	JAL	    04001194
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;
	sp_reg_pc = 0x04001260;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_04001264:	// 4001264: <2063ffff>	ADDI      V1 = V1 + ffff
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;


_04001268:	// 4001268: <09000446>	J         04001118
	goto _04001118;


_0400126C:	// 400126c: <00000000>	NOP       


_04001270:	// 4001270: <97030004>	LHU       V1 = [T8+0004]
	state.r[V1] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_04001274:	// 4001274: <1060ffa8>	BEQ       (R0==V1) --> 1118
	sp_reg_pc = 0x04001274;
	if (state.r[V1] == 0)
	{
		state.r[V0] = ((_u32)state.r[T9] << 8);
		goto _04001118;
	}


_04001278:	// 4001278: <00191200>	SLL       V0 = T9 << 8
	state.r[V0] = ((_u32)state.r[T9] << 8);


_0400127C:	// 400127c: <00021202>	SRL       V0 = V0 >> 8
	state.r[V0] = ((_u32)state.r[V0] >> 8);


_04001280:	// 4001280: <00192602>	SRL       A0 = T9 >> 24
	state.r[A0] = ((_u32)state.r[T9] >> 24);


_04001284:	// 4001284: <00042080>	SLL       A0 = A0 << 2
	state.r[A0] = ((_u32)state.r[A0] << 2);


_04001288:	// 4001288: <8c850320>	LW        A1 = [A0+0320]
	state.r[A1] = (_s32)Load32_DMEM((state.r[A0] + 0x00000320) & 0xfff);


_0400128C:	// 400128c: <00451020>	ADD       V0 = V0+A1
	state.r[V0] = (state.r[V0] + state.r[A1]);


_04001290:	// 4001290: <97010002>	LHU       AT = [T8+0002]
	state.r[AT] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000002) & 0xfff);


_04001294:	// 4001294: <0d000470>	JAL	    040011c0
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;
	sp_reg_pc = 0x04001294;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _040011C0;


_04001298:	// 4001298: <2063ffff>	ADDI      V1 = V1 + ffff
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;


_0400129C:	// 400129c: <09000446>	J         04001118
	goto _04001118;


_040012A0:	// 40012a0: <00000000>	NOP       


_040012A4:	// 40012a4: <00191200>	SLL       V0 = T9 << 8
	state.r[V0] = ((_u32)state.r[T9] << 8);


_040012A8:	// 40012a8: <00021202>	SRL       V0 = V0 >> 8
	state.r[V0] = ((_u32)state.r[V0] >> 8);


_040012AC:	// 40012ac: <00192602>	SRL       A0 = T9 >> 24
	state.r[A0] = ((_u32)state.r[T9] >> 24);


_040012B0:	// 40012b0: <00042080>	SLL       A0 = A0 << 2
	state.r[A0] = ((_u32)state.r[A0] << 2);


_040012B4:	// 40012b4: <8c850320>	LW        A1 = [A0+0320]
	state.r[A1] = (_s32)Load32_DMEM((state.r[A0] + 0x00000320) & 0xfff);


_040012B8:	// 40012b8: <00451020>	ADD       V0 = V0+A1
	state.r[V0] = (state.r[V0] + state.r[A1]);


_040012BC:	// 40012bc: <200104c0>	ADDI      AT = R0 + 04c0
	state.r[AT] = 0 + 0x04C0;


_040012C0:	// 40012c0: <3343ffff>	ANDI      V1 = K0 & ffff
	state.r[V1] = (state.r[K0] & 0x0000FFFF);


_040012C4:	// 40012c4: <0d000465>	JAL	    04001194
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;
	sp_reg_pc = 0x040012C4;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_040012C8:	// 40012c8: <2063ffff>	ADDI      V1 = V1 + ffff
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;


_040012CC:	// 40012cc: <09000446>	J         04001118
	goto _04001118;


_040012D0:	// 40012d0: <00000000>	NOP       


_040012D4:	// 40012d4: <00191a00>	SLL       V1 = T9 << 8
	state.r[V1] = ((_u32)state.r[T9] << 8);


_040012D8:	// 40012d8: <00031a02>	SRL       V1 = V1 >> 8
	state.r[V1] = ((_u32)state.r[V1] >> 8);


_040012DC:	// 40012dc: <00191602>	SRL       V0 = T9 >> 24
	state.r[V0] = ((_u32)state.r[T9] >> 24);


_040012E0:	// 40012e0: <00021080>	SLL       V0 = V0 << 2
	state.r[V0] = ((_u32)state.r[V0] << 2);


_040012E4:	// 40012e4: <00022020>	ADD       A0 = R0+V0
	state.r[A0] = (0 + state.r[V0]);


_040012E8:	// 40012e8: <09000446>	J         04001118
	Save32_DMEM((_u32)state.r[V1], (state.r[A0] + 0x00000320) & 0xfff);
	goto _04001118;


_040012EC:	// 40012ec: <ac830320>	SW        [A0+0320] = V1
	Save32_DMEM((_u32)state.r[V1], (state.r[A0] + 0x00000320) & 0xfff);


_040012F0:	// 40012f0: <234105c0>	ADDI      AT = K0 + 05c0
	state.r[AT] = state.r[K0] + 0x05C0;


_040012F4:	// 40012f4: <00191402>	SRL       V0 = T9 >> 16
	state.r[V0] = ((_u32)state.r[T9] >> 16);


_040012F8:	// 40012f8: <204205c0>	ADDI      V0 = V0 + 05c0
	state.r[V0] = state.r[V0] + 0x05C0;


_040012FC:	// 40012fc: <001a2402>	SRL       A0 = K0 >> 16
	state.r[A0] = ((_u32)state.r[K0] >> 16);


_04001300:	// 4001300: <30840008>	ANDI      A0 = A0 & 0008
	state.r[A0] = (state.r[A0] & 0x00000008);


_04001304:	// 4001304: <1c800005>	BGTZ      (R0>0) --> 131c
	sp_reg_pc = 0x04001304;
	if((_s32)state.r[A0] > 0)
	{
		state.r[V1] = state.r[T9] + 0x05C0;
		goto _0400131C;
	}


_04001308:	// 4001308: <232305c0>	ADDI      V1 = T9 + 05c0
	state.r[V1] = state.r[T9] + 0x05C0;


_0400130C:	// 400130c: <a7010000>	SH        [T8+0000] = AT
	Save16_DMEM((_u16)state.r[AT], (state.r[T8] + 0x00000000) & 0xfff);


_04001310:	// 4001310: <a7020002>	SH        [T8+0002] = V0
	Save16_DMEM((_u16)state.r[V0], (state.r[T8] + 0x00000002) & 0xfff);


_04001314:	// 4001314: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x00000004) & 0xfff);
	goto _04001118;


_04001318:	// 4001318: <a7190004>	SH        [T8+0004] = T9
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x00000004) & 0xfff);


_0400131C:	// 400131c: <a703000e>	SH        [T8+000e] = V1
	Save16_DMEM((_u16)state.r[V1], (state.r[T8] + 0x0000000E) & 0xfff);


_04001320:	// 4001320: <a701000a>	SH        [T8+000a] = AT
	Save16_DMEM((_u16)state.r[AT], (state.r[T8] + 0x0000000A) & 0xfff);


_04001324:	// 4001324: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[V0], (state.r[T8] + 0x0000000C) & 0xfff);
	goto _04001118;


_04001328:	// 4001328: <a702000c>	SH        [T8+000c] = V0
	Save16_DMEM((_u16)state.r[V0], (state.r[T8] + 0x0000000C) & 0xfff);


_0400132C:	// 400132c: <001a1402>	SRL       V0 = K0 >> 16
	state.r[V0] = ((_u32)state.r[K0] >> 16);


_04001330:	// 4001330: <30410008>	ANDI      AT = V0 & 0008
	state.r[AT] = (state.r[V0] & 0x00000008);


_04001334:	// 4001334: <10200004>	BEQ       (R0==AT) --> 1348
	sp_reg_pc = 0x04001334;
	if (state.r[AT] == 0)
	{
		state.r[AT] = (state.r[V0] & 0x00000004);
		goto _04001348;
	}


_04001338:	// 4001338: <30410004>	ANDI      AT = V0 & 0004
	state.r[AT] = (state.r[V0] & 0x00000004);


_0400133C:	// 400133c: <a71a001c>	SH        [T8+001c] = K0
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x0000001C) & 0xfff);


_04001340:	// 4001340: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x0000001E) & 0xfff);
	goto _04001118;


_04001344:	// 4001344: <a719001e>	SH        [T8+001e] = T9
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x0000001E) & 0xfff);


_04001348:	// 4001348: <10200007>	BEQ       (R0==AT) --> 1368
	sp_reg_pc = 0x04001348;
	if (state.r[AT] == 0)
	{
		state.r[AT] = (state.r[V0] & 0x00000002);
		goto _04001368;
	}


_0400134C:	// 400134c: <30410002>	ANDI      AT = V0 & 0002
	state.r[AT] = (state.r[V0] & 0x00000002);


_04001350:	// 4001350: <10200003>	BEQ       (R0==AT) --> 1360
	sp_reg_pc = 0x04001350;
	if (state.r[AT] == 0)
	{
		goto _04001360;
	}


_04001354:	// 4001354: <00000000>	NOP       


_04001358:	// 4001358: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x00000006) & 0xfff);
	goto _04001118;


_0400135C:	// 400135c: <a71a0006>	SH        [T8+0006] = K0
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x00000006) & 0xfff);


_04001360:	// 4001360: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x00000008) & 0xfff);
	goto _04001118;


_04001364:	// 4001364: <a71a0008>	SH        [T8+0008] = K0
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x00000008) & 0xfff);


_04001368:	// 4001368: <10200005>	BEQ       (R0==AT) --> 1380
	sp_reg_pc = 0x04001368;
	if (state.r[AT] == 0)
	{
		state.r[AT] = ((_u32)state.r[T9] >> 16);
		goto _04001380;
	}


_0400136C:	// 400136c: <00190c02>	SRL       AT = T9 >> 16
	state.r[AT] = ((_u32)state.r[T9] >> 16);


_04001370:	// 4001370: <a71a0010>	SH        [T8+0010] = K0
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x00000010) & 0xfff);


_04001374:	// 4001374: <a7010012>	SH        [T8+0012] = AT
	Save16_DMEM((_u16)state.r[AT], (state.r[T8] + 0x00000012) & 0xfff);


_04001378:	// 4001378: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x00000014) & 0xfff);
	goto _04001118;


_0400137C:	// 400137c: <a7190014>	SH        [T8+0014] = T9
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x00000014) & 0xfff);


_04001380:	// 4001380: <a71a0016>	SH        [T8+0016] = K0
	Save16_DMEM((_u16)state.r[K0], (state.r[T8] + 0x00000016) & 0xfff);


_04001384:	// 4001384: <a7010018>	SH        [T8+0018] = AT
	Save16_DMEM((_u16)state.r[AT], (state.r[T8] + 0x00000018) & 0xfff);


_04001388:	// 4001388: <09000446>	J         04001118
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x0000001A) & 0xfff);
	goto _04001118;


_0400138C:	// 400138c: <a719001a>	SH        [T8+001a] = T9
	Save16_DMEM((_u16)state.r[T9], (state.r[T8] + 0x0000001A) & 0xfff);


_04001390:	// 4001390: <97040004>	LHU       A0 = [T8+0004]
	state.r[A0] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_04001394:	// 4001394: <97030002>	LHU       V1 = [T8+0002]
	state.r[V1] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000002) & 0xfff);


_04001398:	// 4001398: <1080ff5f>	BEQ       (R0==A0) --> 1118
	sp_reg_pc = 0x04001398;
	if (state.r[A0] == 0)
	{
		state.r[V0] = (state.r[T9] & 0x0000FFFF);
		goto _04001118;
	}


_0400139C:	// 400139c: <3322ffff>	ANDI      V0 = T9 & ffff
	state.r[V0] = (state.r[T9] & 0x0000FFFF);


_040013A0:	// 40013a0: <204205c0>	ADDI      V0 = V0 + 05c0
	state.r[V0] = state.r[V0] + 0x05C0;


_040013A4:	// 40013a4: <00190c02>	SRL       AT = T9 >> 16
	state.r[AT] = ((_u32)state.r[T9] >> 16);


_040013A8:	// 40013a8: <202105c0>	ADDI      AT = AT + 05c0
	state.r[AT] = state.r[AT] + 0x05C0;


_040013AC:	// 40013ac: <12c00005>	BEQ       (R0==S6) --> 13c4
	sp_reg_pc = 0x040013AC;
	if (state.r[S6] == 0)
	{
		goto _040013C4;
	}


_040013B0:	// 40013b0: <00000000>	NOP       


_040013B4:	// 40013b4: <40053000>	MFC0      A2 = SP DMA full
	state.r[A1] = 0;


_040013B8:	// 40013b8: <14a0fffe>	BNE       (R0!=A1) --> 13b4
	sp_reg_pc = 0x040013B8;
	if (state.r[A1] != 0)
	{
		goto _040013B4;
	}


_040013BC:	// 40013bc: <00000000>	NOP       


_040013C0:	// 40013c0: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_040013C4:	// 40013c4: <c8212000>	LQV       vec01 <00> = [AT + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[1].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[1].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[1].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[1].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[1].U64[0] = state.v[1].U64[0] & ~temp1;
			state.v[1].U64[1] = state.v[1].U64[1] & ~temp2;
			state.v[1].U64[0] = state.v[1].U64[0] | value1;
			state.v[1].U64[1] = state.v[1].U64[1] | value2;
		}
	}


_040013C8:	// 40013c8: <c8422000>	LQV       vec02 <00> = [V0 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[2].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[2].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[2].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[2].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[2].U64[0] = state.v[2].U64[0] & ~temp1;
			state.v[2].U64[1] = state.v[2].U64[1] & ~temp2;
			state.v[2].U64[0] = state.v[2].U64[0] | value1;
			state.v[2].U64[1] = state.v[2].U64[1] | value2;
		}
	}


_040013CC:	// 40013cc: <e8610800>	SSV       [V1 + 0x00] = vec01 <00>
	Save16_DMEM(state.v[1].U16[7], (0x00000000 + state.r[V1]) & 0xfff);


_040013D0:	// 40013d0: <e8620801>	SSV       [V1 + 0x02] = vec02 <00>
	Save16_DMEM(state.v[2].U16[7], (0x00000002 + state.r[V1]) & 0xfff);


_040013D4:	// 40013d4: <e8610902>	SSV       [V1 + 0x04] = vec01 <02>
	Save16_DMEM(state.v[1].U16[6], (0x00000004 + state.r[V1]) & 0xfff);


_040013D8:	// 40013d8: <e8620903>	SSV       [V1 + 0x06] = vec02 <02>
	Save16_DMEM(state.v[2].U16[6], (0x00000006 + state.r[V1]) & 0xfff);


_040013DC:	// 40013dc: <e8610a04>	SSV       [V1 + 0x08] = vec01 <04>
	Save16_DMEM(state.v[1].U16[5], (0x00000008 + state.r[V1]) & 0xfff);


_040013E0:	// 40013e0: <e8620a05>	SSV       [V1 + 0x0a] = vec02 <04>
	Save16_DMEM(state.v[2].U16[5], (0x0000000A + state.r[V1]) & 0xfff);


_040013E4:	// 40013e4: <e8610b06>	SSV       [V1 + 0x0c] = vec01 <06>
	Save16_DMEM(state.v[1].U16[4], (0x0000000C + state.r[V1]) & 0xfff);


_040013E8:	// 40013e8: <e8620b07>	SSV       [V1 + 0x0e] = vec02 <06>
	Save16_DMEM(state.v[2].U16[4], (0x0000000E + state.r[V1]) & 0xfff);


_040013EC:	// 40013ec: <e8610c08>	SSV       [V1 + 0x10] = vec01 <08>
	Save16_DMEM(state.v[1].U16[3], (0x00000010 + state.r[V1]) & 0xfff);


_040013F0:	// 40013f0: <e8620c09>	SSV       [V1 + 0x12] = vec02 <08>
	Save16_DMEM(state.v[2].U16[3], (0x00000012 + state.r[V1]) & 0xfff);


_040013F4:	// 40013f4: <e8610d0a>	SSV       [V1 + 0x14] = vec01 <10>
	Save16_DMEM(state.v[1].U16[2], (0x00000014 + state.r[V1]) & 0xfff);


_040013F8:	// 40013f8: <e8620d0b>	SSV       [V1 + 0x16] = vec02 <10>
	Save16_DMEM(state.v[2].U16[2], (0x00000016 + state.r[V1]) & 0xfff);


_040013FC:	// 40013fc: <e8610e0c>	SSV       [V1 + 0x18] = vec01 <12>
	Save16_DMEM(state.v[1].U16[1], (0x00000018 + state.r[V1]) & 0xfff);


_04001400:	// 4001400: <e8620e0d>	SSV       [V1 + 0x1a] = vec02 <12>
	Save16_DMEM(state.v[2].U16[1], (0x0000001A + state.r[V1]) & 0xfff);


_04001404:	// 4001404: <e8610f0e>	SSV       [V1 + 0x1c] = vec01 <14>
	Save16_DMEM(state.v[1].U16[0], (0x0000001C + state.r[V1]) & 0xfff);


_04001408:	// 4001408: <e8620f0f>	SSV       [V1 + 0x1e] = vec02 <14>
	Save16_DMEM(state.v[2].U16[0], (0x0000001E + state.r[V1]) & 0xfff);


_0400140C:	// 400140c: <2084fff0>	ADDI      A0 = A0 + fff0
	state.r[A0] = state.r[A0] + 0xFFFFFFF0;


_04001410:	// 4001410: <20210010>	ADDI      AT = AT + 0010
	state.r[AT] = state.r[AT] + 0x0010;


_04001414:	// 4001414: <20420010>	ADDI      V0 = V0 + 0010
	state.r[V0] = state.r[V0] + 0x0010;


_04001418:	// 4001418: <1c80ffea>	BGTZ      (R0>0) --> 13c4
	sp_reg_pc = 0x04001418;
	if((_s32)state.r[A0] > 0)
	{
		state.r[V1] = state.r[V1] + 0x0020;
		goto _040013C4;
	}


_0400141C:	// 400141c: <20630020>	ADDI      V1 = V1 + 0020
	state.r[V1] = state.r[V1] + 0x0020;


_04001420:	// 4001420: <09000446>	J         04001118
	goto _04001118;


_04001424:	// 4001424: <00000000>	NOP       


_04001428:	// 4001428: <3323ffff>	ANDI      V1 = T9 & ffff
	state.r[V1] = (state.r[T9] & 0x0000FFFF);


_0400142C:	// 400142c: <1060ff3a>	BEQ       (R0==V1) --> 1118
	sp_reg_pc = 0x0400142C;
	if (state.r[V1] == 0)
	{
		state.r[AT] = (state.r[K0] & 0x0000FFFF);
		goto _04001118;
	}


_04001430:	// 4001430: <3341ffff>	ANDI      AT = K0 & ffff
	state.r[AT] = (state.r[K0] & 0x0000FFFF);


_04001434:	// 4001434: <202105c0>	ADDI      AT = AT + 05c0
	state.r[AT] = state.r[AT] + 0x05C0;


_04001438:	// 4001438: <00191402>	SRL       V0 = T9 >> 16
	state.r[V0] = ((_u32)state.r[T9] >> 16);


_0400143C:	// 400143c: <204205c0>	ADDI      V0 = V0 + 05c0
	state.r[V0] = state.r[V0] + 0x05C0;


_04001440:	// 4001440: <12c00005>	BEQ       (R0==S6) --> 1458
	sp_reg_pc = 0x04001440;
	if (state.r[S6] == 0)
	{
		goto _04001458;
	}


_04001444:	// 4001444: <00000000>	NOP       


_04001448:	// 4001448: <40043000>	MFC0      A2 = SP status
	state.r[A0] = 0;


_0400144C:	// 400144c: <1480fffe>	BNE       (R0!=A0) --> 1448
	sp_reg_pc = 0x0400144C;
	if (state.r[A0] != 0)
	{
		goto _04001448;
	}


_04001450:	// 4001450: <00000000>	NOP       


_04001454:	// 4001454: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_04001458:	// 4001458: <c8211800>	LDV       vec01 <00> = [AT + 0x00]

	// [start function: DKR1458_1474]

	DKR1458_1474();
	goto _04001478;

_0400145C:	// 400145c: <c8221801>	LDV       vec02 <00> = [AT + 0x08]

_04001460:	// 4001460: <2063fff0>	ADDI      V1 = V1 + fff0

_04001464:	// 4001464: <20210010>	ADDI      AT = AT + 0010

_04001468:	// 4001468: <e8411800>	SDV       [V0 + 0x00] = vec01 <00>

_0400146C:	// 400146c: <e8421801>	SDV       [V0 + 0x04] = vec02 <00>

_04001470:	// 4001470: <1c60fff9>	BGTZ      (R0>0) --> 1458

_04001474:	// 4001474: <20420010>	ADDI      V0 = V0 + 0010
	ErrorToCallFunction(0x04001474);

	// [end of function: DKR1458_1474]

_04001478:	// 4001478: <09000446>	J         04001118
	goto _04001118;


_0400147C:	// 400147c: <00000000>	NOP       


_04001480:	// 4001480: <00190a00>	SLL       AT = T9 << 8
	state.r[AT] = ((_u32)state.r[T9] << 8);


_04001484:	// 4001484: <00010a02>	SRL       AT = AT >> 8
	state.r[AT] = ((_u32)state.r[AT] >> 8);


_04001488:	// 4001488: <00191e02>	SRL       V1 = T9 >> 24
	state.r[V1] = ((_u32)state.r[T9] >> 24);


_0400148C:	// 400148c: <00031880>	SLL       V1 = V1 << 2
	state.r[V1] = ((_u32)state.r[V1] << 2);


_04001490:	// 4001490: <8c620320>	LW        V0 = [V1+0320]
	state.r[V0] = (_s32)Load32_DMEM((state.r[V1] + 0x00000320) & 0xfff);


_04001494:	// 4001494: <00220820>	ADD       AT = AT+V0
	state.r[AT] = (state.r[AT] + state.r[V0]);


_04001498:	// 4001498: <af010010>	SW        [T8+0010] = AT
	Save32_DMEM((_u32)state.r[AT], (state.r[T8] + 0x00000010) & 0xfff);


_0400149C:	// 400149c: <09000446>	J         04001118
	goto _04001118;


_040014A0:	// 40014a0: <00000000>	NOP       


_040014A4:	// 40014a4: <c81f2000>	LQV       vec31 <00> = [R0 + 0x00]
	{
		_u32 addr = (0x00000000 + 0);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[31].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[31].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[31].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[31].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[31].U64[0] = state.v[31].U64[0] & ~temp1;
			state.v[31].U64[1] = state.v[31].U64[1] & ~temp2;
			state.v[31].U64[0] = state.v[31].U64[0] | value1;
			state.v[31].U64[1] = state.v[31].U64[1] | value2;
		}
	}


_040014A8:	// 40014a8: <4a1bdeec>	VXOR      vec27 = vec27 xor vec27[<none>]
	rsp_cop2_vxor(&state.v[27], &state.v[27], &state.v[27]);


_040014AC:	// 40014ac: <97150000>	LHU       S5 = [T8+0000]
	state.r[S5] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000000) & 0xfff);


_040014B0:	// 40014b0: <4a19ce6c>	VXOR      vec25 = vec25 xor vec25[<none>]
	rsp_cop2_vxor(&state.v[25], &state.v[25], &state.v[25]);


_040014B4:	// 40014b4: <4a18c62c>	VXOR      vec24 = vec24 xor vec24[<none>]
	rsp_cop2_vxor(&state.v[24], &state.v[24], &state.v[24]);


_040014B8:	// 40014b8: <22b40001>	ADDI      S4 = S5 + 0001
	state.r[S4] = state.r[S5] + 0x0001;


_040014BC:	// 40014bc: <97130002>	LHU       S3 = [T8+0002]
	state.r[S3] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000002) & 0xfff);


_040014C0:	// 40014c0: <4a0d6b6c>	VXOR      vec13 = vec13 xor vec13[<none>]
	rsp_cop2_vxor(&state.v[13], &state.v[13], &state.v[13]);


_040014C4:	// 40014c4: <4a0e73ac>	VXOR      vec14 = vec14 xor vec14[<none>]
	rsp_cop2_vxor(&state.v[14], &state.v[14], &state.v[14]);


_040014C8:	// 40014c8: <97120004>	LHU       S2 = [T8+0004]
	state.r[S2] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_040014CC:	// 40014cc: <4a0f7bec>	VXOR      vec15 = vec15 xor vec15[<none>]
	rsp_cop2_vxor(&state.v[15], &state.v[15], &state.v[15]);


_040014D0:	// 40014d0: <3c0100ff>	LUI       AT = 0x00ff0000
	state.r[AT] = 0x00FF0000;


_040014D4:	// 40014d4: <4a10842c>	VXOR      vec16 = vec16 xor vec16[<none>]
	rsp_cop2_vxor(&state.v[16], &state.v[16], &state.v[16]);


_040014D8:	// 40014d8: <3421ffff>	ORI       AT = AT | 0xffff
	state.r[AT] = (state.r[AT] | 0x0000FFFF);


_040014DC:	// 40014dc: <4a118c6c>	VXOR      vec17 = vec17 xor vec17[<none>]
	rsp_cop2_vxor(&state.v[17], &state.v[17], &state.v[17]);


_040014E0:	// 40014e0: <03218824>	AND       S1 = T9 & AT
	state.r[S1] = (state.r[T9] & state.r[AT]);


_040014E4:	// 40014e4: <4a1294ac>	VXOR      vec18 = vec18 xor vec18[<none>]
	rsp_cop2_vxor(&state.v[18], &state.v[18], &state.v[18]);


_040014E8:	// 40014e8: <00191602>	SRL       V0 = T9 >> 24
	state.r[V0] = ((_u32)state.r[T9] >> 24);


_040014EC:	// 40014ec: <4a139cec>	VXOR      vec19 = vec19 xor vec19[<none>]
	rsp_cop2_vxor(&state.v[19], &state.v[19], &state.v[19]);


_040014F0:	// 40014f0: <00021080>	SLL       V0 = V0 << 2
	state.r[V0] = ((_u32)state.r[V0] << 2);


_040014F4:	// 40014f4: <8c430320>	LW        V1 = [V0+0320]
	state.r[V1] = (_s32)Load32_DMEM((state.r[V0] + 0x00000320) & 0xfff);


_040014F8:	// 40014f8: <02238820>	ADD       S1 = S1+V1
	state.r[S1] = (state.r[S1] + state.r[V1]);


_040014FC:	// 40014fc: <ea7b2000>	SQV       [S3 + 0x00] = vec27 <00>
	{
		_u32    addr = (0x00000000 + state.r[S3]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[27].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[27].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[27].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[27].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[27].U64[0] & temp1);
			value2 |= (state.v[27].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001500:	// 4001500: <ea7b2001>	SQV       [S3 + 0x10] = vec27 <00>
	{
		_u32    addr = (0x00000010 + state.r[S3]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[27].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[27].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[27].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[27].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[27].U64[0] & temp1);
			value2 |= (state.v[27].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001504:	// 4001504: <001a0c02>	SRL       AT = K0 >> 16
	state.r[AT] = ((_u32)state.r[K0] >> 16);


_04001508:	// 4001508: <30210001>	ANDI      AT = AT & 0001
	state.r[AT] = (state.r[AT] & 0x00000001);


_0400150C:	// 400150c: <1c20000c>	BGTZ      (R0>0) --> 1540
	sp_reg_pc = 0x0400150C;
	if((_s32)state.r[AT] > 0)
	{
		state.r[AT] = ((_u32)state.r[K0] >> 16);
		goto _04001540;
	}


_04001510:	// 4001510: <001a0c02>	SRL       AT = K0 >> 16
	state.r[AT] = ((_u32)state.r[K0] >> 16);


_04001514:	// 4001514: <30210002>	ANDI      AT = AT & 0002
	state.r[AT] = (state.r[AT] & 0x00000002);


_04001518:	// 4001518: <10010002>	BEQ       (AT==R0) --> 1524
	sp_reg_pc = 0x04001518;
	if (0 == state.r[AT])
	{
		state.r[V0] = state.r[S1] + 0x0000;
		goto _04001524;
	}


_0400151C:	// 400151c: <22220000>	ADDI      V0 = S1 + 0000
	state.r[V0] = state.r[S1] + 0x0000;


_04001520:	// 4001520: <8f020010>	LW        V0 = [T8+0010]
	state.r[V0] = (_s32)Load32_DMEM((state.r[T8] + 0x00000010) & 0xfff);


_04001524:	// 4001524: <22610000>	ADDI      AT = S3 + 0000
	state.r[AT] = state.r[S3] + 0x0000;


_04001528:	// 4001528: <0d000465>	JAL	    04001194
	state.r[V1] = 0 + 0x001F;
	sp_reg_pc = 0x04001528;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_0400152C:	// 400152c: <2003001f>	ADDI      V1 = R0 + 001f
	state.r[V1] = 0 + 0x001F;


_04001530:	// 4001530: <40053000>	MFC0      A2 = SP DMA full
	state.r[A1] = 0;


_04001534:	// 4001534: <14a0fffe>	BNE       (R0!=A1) --> 1530
	sp_reg_pc = 0x04001534;
	if (state.r[A1] != 0)
	{
		goto _04001530;
	}


_04001538:	// 4001538: <00000000>	NOP       


_0400153C:	// 400153c: <0000b020>	ADD       S6 = R0+R0
	state.r[S6] = (0 + 0);


_04001540:	// 4001540: <12c00005>	BEQ       (R0==S6) --> 1558
	sp_reg_pc = 0x04001540;
	if (state.r[S6] == 0)
	{
		goto _04001558;
	}


_04001544:	// 4001544: <00000000>	NOP       


_04001548:	// 4001548: <40013000>	MFC0      A2 = SP DRAM DMA address
	state.r[AT] = 0;


_0400154C:	// 400154c: <1420fffe>	BNE       (R0!=AT) --> 1548
	sp_reg_pc = 0x0400154C;
	if (state.r[AT] != 0)
	{
		goto _04001548;
	}


_04001550:	// 4001550: <00000000>	NOP       


_04001554:	// 4001554: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_04001558:	// 4001558: <20100030>	ADDI      S0 = R0 + 0030
	state.r[S0] = 0 + 0x0030;


_0400155C:	// 400155c: <200f04c0>	ADDI      T7 = R0 + 04c0
	state.r[T7] = 0 + 0x04C0;


_04001560:	// 4001560: <ca191800>	LDV       vec25 <00> = [S0 + 0x00]
	rsp_ldv_compiler((state.r[S0] & 0xFFF), 25, 8);


_04001564:	// 4001564: <ca181c00>	LDV       vec24 <08> = [S0 + 0x00]
	rsp_ldv_compiler((state.r[S0] & 0xFFF), 24, 0);


_04001568:	// 4001568: <ca171801>	LDV       vec23 <00> = [S0 + 0x08]
	rsp_ldv_compiler((state.r[S0] + 0x00000008) & 0xFFF, 23, 8);


_0400156C:	// 400156c: <ca171c01>	LDV       vec23 <08> = [S0 + 0x08]
	rsp_ldv_compiler((state.r[S0] + 0x00000008) & 0xFFF, 23, 0);


_04001570:	// 4001570: <ca7b2001>	LQV       vec27 <00> = [S3 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[S3]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}


_04001574:	// 4001574: <22730020>	ADDI      S3 = S3 + 0020
	state.r[S3] = state.r[S3] + 0x0020;


_04001578:	// 4001578: <1240006e>	BEQ       (R0==S2) --> 1734
	sp_reg_pc = 0x04001578;
	if (state.r[S2] == 0)
	{
		rsp_ldv_compiler((state.r[S4] & 0xFFF), 1, 8);
		goto _04001734;
	}


_0400157C:	// 400157c: <ca811800>	LDV       vec01 <00> = [S4 + 0x00]
	rsp_ldv_compiler((state.r[S4] & 0xFFF), 1, 8);


_04001580:	// 4001580: <92a10000>	LBU       AT = [S5+0000]
	state.r[AT] = (_s32)(_u8)pDMEM[((state.r[S5] + 0x00000000) & 0xfff) ^ 3];


_04001584:	// 4001584: <302b000f>	ANDI      T3 = AT & 000f
	state.r[T3] = (state.r[AT] & 0x0000000F);


_04001588:	// 4001588: <000b5940>	SLL       T3 = T3 << 5
	state.r[T3] = ((_u32)state.r[T3] << 5);


_0400158C:	// 400158c: <4b01c8e8>	VAND      vec03 = vec25 and vec01[0]
	rsp_cop2_vand_element(&state.v[3], &state.v[25], &state.v[1].U16[7]);


_04001590:	// 4001590: <016f6820>	ADD       T5 = T3+T7
	state.r[T5] = (state.r[T3] + state.r[T7]);


_04001594:	// 4001594: <4b21c128>	VAND      vec04 = vec24 and vec01[1]
	rsp_cop2_vand_element(&state.v[4], &state.v[24], &state.v[1].U16[6]);


_04001598:	// 4001598: <00017102>	SRL       T6 = AT >> 4
	state.r[T6] = ((_u32)state.r[AT] >> 4);


_0400159C:	// 400159c: <4b41c968>	VAND      vec05 = vec25 and vec01[2]
	rsp_cop2_vand_element(&state.v[5], &state.v[25], &state.v[1].U16[5]);


_040015A0:	// 40015a0: <2002000c>	ADDI      V0 = R0 + 000c
	state.r[V0] = 0 + 0x000C;


_040015A4:	// 40015a4: <4b61c1a8>	VAND      vec06 = vec24 and vec01[3]
	rsp_cop2_vand_element(&state.v[6], &state.v[24], &state.v[1].U16[4]);


_040015A8:	// 40015a8: <004e7022>	SUB       T6 = V0-T6
	state.r[T6] = (state.r[V0] - state.r[T6]);


_040015AC:	// 40015ac: <21c2ffff>	ADDI      V0 = T6 + ffff
	state.r[V0] = state.r[T6] + 0xFFFFFFFF;


_040015B0:	// 40015b0: <20030001>	ADDI      V1 = R0 + 0001
	state.r[V1] = 0 + 0x0001;


_040015B4:	// 40015b4: <00031bc0>	SLL       V1 = V1 << 15
	state.r[V1] = ((_u32)state.r[V1] << 15);


_040015B8:	// 40015b8: <00432006>	SRLV      V1 = A0 >> V0
	state.r[A0] = ((_u32)state.r[V1] >> (state.r[V0] & 0x1F));


_040015BC:	// 40015bc: <4884b000>	MTC2      vec22 <00> = A0
	state.v[22].U16[7] = (_u16)state.r[A0];


_040015C0:	// 40015c0: <c9b52000>	LQV       vec21 <00> = [T5 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[T5]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[21].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[21].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[21].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[21].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[21].U64[0] = state.v[21].U64[0] & ~temp1;
			state.v[21].U64[1] = state.v[21].U64[1] & ~temp2;
			state.v[21].U64[0] = state.v[21].U64[0] | value1;
			state.v[21].U64[1] = state.v[21].U64[1] | value2;
		}
	}


_040015C4:	// 40015c4: <c9b42001>	LQV       vec20 <00> = [T5 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[T5]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[20].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[20].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[20].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[20].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[20].U64[0] = state.v[20].U64[0] & ~temp1;
			state.v[20].U64[1] = state.v[20].U64[1] & ~temp2;
			state.v[20].U64[0] = state.v[20].U64[0] | value1;
			state.v[20].U64[1] = state.v[20].U64[1] | value2;
		}
	}


_040015C8:	// 40015c8: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015CC:	// 40015cc: <c9b32802>	LRV       vec19 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[19].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_040015D0:	// 40015d0: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015D4:	// 40015d4: <c9b22802>	LRV       vec18 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[18].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_040015D8:	// 40015d8: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015DC:	// 40015dc: <c9b12802>	LRV       vec17 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[17].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_040015E0:	// 40015e0: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015E4:	// 40015e4: <c9b02802>	LRV       vec16 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[16].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_040015E8:	// 40015e8: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015EC:	// 40015ec: <c9af2802>	LRV       vec15 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[15].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_040015F0:	// 40015f0: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015F4:	// 40015f4: <c9ae2802>	LRV       vec14 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[14].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_040015F8:	// 40015f8: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_040015FC:	// 40015fc: <c9ad2802>	LRV       vec13 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[13].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_04001600:	// 4001600: <22940009>	ADDI      S4 = S4 + 0009
	state.r[S4] = state.r[S4] + 0x0009;


_04001604:	// 4001604: <4a171f86>	VMUDN     vec30 = ( acc = vec03 * vec23[<none>]      ) >> 16
	// In function: Mario15B8_16DC
	//Call the function: Mario15B8_16DC
	Mario15B8_16DC();
	goto _0400172C;

_04001608:	// 4001608: <22b50009>	ADDI      S5 = S5 + 0009
	ErrorToCallFunction(0x04001608);

_0400160C:	// 400160c: <4a17278e>	VMADN     vec30 = ( acc+= vec04 * vec23[<none>] )
	ErrorToCallFunction(0x0400160C);

_04001610:	// 4001610: <ca811800>	LDV       vec01 <00> = [S4 + 0x00]
	ErrorToCallFunction(0x04001610);

_04001614:	// 4001614: <4a172f46>	VMUDN     vec29 = ( acc = vec05 * vec23[<none>]      ) >> 16
	ErrorToCallFunction(0x04001614);

_04001618:	// 4001618: <92a10000>	LBU       AT = [S5+0000]
	ErrorToCallFunction(0x04001618);

_0400161C:	// 400161c: <4a17374e>	VMADN     vec29 = ( acc+= vec06 * vec23[<none>] )
	ErrorToCallFunction(0x0400161C);

_04001620:	// 4001620: <19c00003>	BLEZ      (R0<=0) --> 1630
	ErrorToCallFunction(0x04001620);

_04001624:	// 4001624: <302b000f>	ANDI      T3 = AT & 000f
	ErrorToCallFunction(0x04001624);

_04001628:	// 4001628: <4b16f785>	VMUDM     vec30 = ( acc = vec30 * vec22[0] ) >> 16
	ErrorToCallFunction(0x04001628);

_0400162C:	// 400162c: <4b16ef45>	VMUDM     vec29 = ( acc = vec29 * vec22[0] ) >> 16
	ErrorToCallFunction(0x0400162C);

_04001630:	// 4001630: <000b5940>	SLL       T3 = T3 << 5
	ErrorToCallFunction(0x04001630);

_04001634:	// 4001634: <4b01c8e8>	VAND      vec03 = vec25 and vec01[0]
	ErrorToCallFunction(0x04001634);

_04001638:	// 4001638: <016f6820>	ADD       T5 = T3+T7
	ErrorToCallFunction(0x04001638);

_0400163C:	// 400163c: <4b21c128>	VAND      vec04 = vec24 and vec01[1]
	ErrorToCallFunction(0x0400163C);

_04001640:	// 4001640: <4b41c968>	VAND      vec05 = vec25 and vec01[2]
	ErrorToCallFunction(0x04001640);

_04001644:	// 4001644: <4b61c1a8>	VAND      vec06 = vec24 and vec01[3]
	ErrorToCallFunction(0x04001644);

_04001648:	// 4001648: <00017102>	SRL       T6 = AT >> 4
	ErrorToCallFunction(0x04001648);

_0400164C:	// 400164c: <4bdba887>	VMUDH     vec02 = ( acc = (vec21 * vec27[6]) << 16) >> 16
	ErrorToCallFunction(0x0400164C);

_04001650:	// 4001650: <2002000c>	ADDI      V0 = R0 + 000c
	ErrorToCallFunction(0x04001650);

_04001654:	// 4001654: <4bfba08f>	VMADH     vec02 = ( acc+= (vec20 * vec27[7]) << 16) >> 16
	ErrorToCallFunction(0x04001654);

_04001658:	// 4001658: <004e7022>	SUB       T6 = V0-T6
	ErrorToCallFunction(0x04001658);

_0400165C:	// 400165c: <4b1e988f>	VMADH     vec02 = ( acc+= (vec19 * vec30[0]) << 16) >> 16
	ErrorToCallFunction(0x0400165C);

_04001660:	// 4001660: <21c2ffff>	ADDI      V0 = T6 + ffff
	ErrorToCallFunction(0x04001660);

_04001664:	// 4001664: <4b3e908f>	VMADH     vec02 = ( acc+= (vec18 * vec30[1]) << 16) >> 16
	ErrorToCallFunction(0x04001664);

_04001668:	// 4001668: <20030001>	ADDI      V1 = R0 + 0001
	ErrorToCallFunction(0x04001668);

_0400166C:	// 400166c: <4b5e888f>	VMADH     vec02 = ( acc+= (vec17 * vec30[2]) << 16) >> 16
	ErrorToCallFunction(0x0400166C);

_04001670:	// 4001670: <00031bc0>	SLL       V1 = V1 << 15
	ErrorToCallFunction(0x04001670);

_04001674:	// 4001674: <4b7e808f>	VMADH     vec02 = ( acc+= (vec16 * vec30[3]) << 16) >> 16
	ErrorToCallFunction(0x04001674);

_04001678:	// 4001678: <00432006>	SRLV      V1 = A0 >> V0
	ErrorToCallFunction(0x04001678);

_0400167C:	// 400167c: <4b9e7f0f>	VMADH     vec28 = ( acc+= (vec15 * vec30[4]) << 16) >> 16
	ErrorToCallFunction(0x0400167C);

_04001680:	// 4001680: <4884b000>	MTC2      vec22 <00> = A0
	ErrorToCallFunction(0x04001680);

_04001684:	// 4001684: <4bbe708f>	VMADH     vec02 = ( acc+= (vec14 * vec30[5]) << 16) >> 16
	ErrorToCallFunction(0x04001684);

_04001688:	// 4001688: <4bde688f>	VMADH     vec02 = ( acc+= (vec13 * vec30[6]) << 16) >> 16
	ErrorToCallFunction(0x04001688);

_0400168C:	// 400168c: <4bbff08f>	VMADH     vec02 = ( acc+= (vec30 * vec31[5]) << 16) >> 16
	ErrorToCallFunction(0x0400168C);

_04001690:	// 4001690: <4b3c3e9d>	VSAW $v26, $v7, $v28[[1]]
	ErrorToCallFunction(0x04001690);

_04001694:	// 4001694: <4b1c3f1d>	VSAW $v28, $v7, $v28[[0]]
	ErrorToCallFunction(0x04001694);

_04001698:	// 4001698: <4b9fd086>	VMUDN     vec02 = ( acc = vec26 * vec31[4]      ) >> 16
	ErrorToCallFunction(0x04001698);

_0400169C:	// 400169c: <4b9fe70f>	VMADH     vec28 = ( acc+= (vec28 * vec31[4]) << 16) >> 16
	ErrorToCallFunction(0x0400169C);

_040016A0:	// 40016a0: <4b1d9887>	VMUDH     vec02 = ( acc = (vec19 * vec29[0]) << 16) >> 16
	ErrorToCallFunction(0x040016A0);

_040016A4:	// 40016a4: <21acfffe>	ADDI      T4 = T5 + fffe
	ErrorToCallFunction(0x040016A4);

_040016A8:	// 40016a8: <4b3d908f>	VMADH     vec02 = ( acc+= (vec18 * vec29[1]) << 16) >> 16
	ErrorToCallFunction(0x040016A8);

_040016AC:	// 40016ac: <c9932802>	LRV       vec19 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x040016AC);

_040016B0:	// 40016b0: <4b5d888f>	VMADH     vec02 = ( acc+= (vec17 * vec29[2]) << 16) >> 16
	ErrorToCallFunction(0x040016B0);

_040016B4:	// 40016b4: <218cfffe>	ADDI      T4 = T4 + fffe
	ErrorToCallFunction(0x040016B4);

_040016B8:	// 40016b8: <4b7d808f>	VMADH     vec02 = ( acc+= (vec16 * vec29[3]) << 16) >> 16
	ErrorToCallFunction(0x040016B8);

_040016BC:	// 40016bc: <c9922802>	LRV       vec18 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x040016BC);

_040016C0:	// 40016c0: <4b9d788f>	VMADH     vec02 = ( acc+= (vec15 * vec29[4]) << 16) >> 16
	ErrorToCallFunction(0x040016C0);

_040016C4:	// 40016c4: <218cfffe>	ADDI      T4 = T4 + fffe
	ErrorToCallFunction(0x040016C4);

_040016C8:	// 40016c8: <4bbd708f>	VMADH     vec02 = ( acc+= (vec14 * vec29[5]) << 16) >> 16
	ErrorToCallFunction(0x040016C8);

_040016CC:	// 40016cc: <c9912802>	LRV       vec17 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x040016CC);

_040016D0:	// 40016d0: <4bdd688f>	VMADH     vec02 = ( acc+= (vec13 * vec29[6]) << 16) >> 16
	ErrorToCallFunction(0x040016D0);

_040016D4:	// 40016d4: <218cfffe>	ADDI      T4 = T4 + fffe
	ErrorToCallFunction(0x040016D4);

_040016D8:	// 40016d8: <4bbfe88f>	VMADH     vec02 = ( acc+= (vec29 * vec31[5]) << 16) >> 16
	ErrorToCallFunction(0x040016D8);

_040016DC:	// 40016dc: <c9902802>	LRV       vec16 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x040016DC);

_040016E0:	// 40016e0: <4bdca88f>	VMADH     vec02 = ( acc+= (vec21 * vec28[6]) << 16) >> 16
	ErrorToCallFunction(0x040016E0);

_040016E4:	// 40016e4: <218cfffe>	ADDI      T4 = T4 + fffe
	ErrorToCallFunction(0x040016E4);

_040016E8:	// 40016e8: <4bfca08f>	VMADH     vec02 = ( acc+= (vec20 * vec28[7]) << 16) >> 16
	ErrorToCallFunction(0x040016E8);

_040016EC:	// 40016ec: <c98f2802>	LRV       vec15 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x040016EC);

_040016F0:	// 40016f0: <4b3b3e9d>	VSAW $v26, $v7, $v27[[1]]
	ErrorToCallFunction(0x040016F0);

_040016F4:	// 40016f4: <218cfffe>	ADDI      T4 = T4 + fffe
	ErrorToCallFunction(0x040016F4);

_040016F8:	// 40016f8: <4b1b3edd>	VSAW $v27, $v7, $v27[[0]]
	ErrorToCallFunction(0x040016F8);

_040016FC:	// 40016fc: <c98e2802>	LRV       vec14 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x040016FC);

_04001700:	// 4001700: <218cfffe>	ADDI      T4 = T4 + fffe
	ErrorToCallFunction(0x04001700);

_04001704:	// 4001704: <c98d2802>	LRV       vec13 <00> = [T4 + 0x20]
	ErrorToCallFunction(0x04001704);

_04001708:	// 4001708: <c9b52000>	LQV       vec21 <00> = [T5 + 0x00]
	ErrorToCallFunction(0x04001708);

_0400170C:	// 400170c: <4b9fd086>	VMUDN     vec02 = ( acc = vec26 * vec31[4]      ) >> 16
	ErrorToCallFunction(0x0400170C);

_04001710:	// 4001710: <c9b42001>	LQV       vec20 <00> = [T5 + 0x10]
	ErrorToCallFunction(0x04001710);

_04001714:	// 4001714: <4b9fdecf>	VMADH     vec27 = ( acc+= (vec27 * vec31[4]) << 16) >> 16
	ErrorToCallFunction(0x04001714);

_04001718:	// 4001718: <2252ffe0>	ADDI      S2 = S2 + ffe0
	ErrorToCallFunction(0x04001718);

_0400171C:	// 400171c: <ea7c1800>	SDV       [S3 + 0x00] = vec28 <00>
	ErrorToCallFunction(0x0400171C);

_04001720:	// 4001720: <ea7c1c01>	SDV       [S3 + 0x04] = vec28 <08>
	ErrorToCallFunction(0x04001720);

_04001724:	// 4001724: <ea7b1802>	SDV       [S3 + 0x08] = vec27 <00>
	ErrorToCallFunction(0x04001724);

_04001728:	// 4001728: <ea7b1c03>	SDV       [S3 + 0x0c] = vec27 <08>
	ErrorToCallFunction(0x04001728);

_0400172C:	// 400172c: <1e40ffb4>	BGTZ      (R0>0) --> 1600
	sp_reg_pc = 0x0400172C;
	if((_s32)state.r[S2] > 0)
	{
		state.r[S3] = state.r[S3] + 0x0020;
		goto _04001600;
	}


_04001730:	// 4001730: <22730020>	ADDI      S3 = S3 + 0020
	state.r[S3] = state.r[S3] + 0x0020;


_04001734:	// 4001734: <2261ffe0>	ADDI      AT = S3 + ffe0
	state.r[AT] = state.r[S3] + 0xFFFFFFE0;


_04001738:	// 4001738: <22220000>	ADDI      V0 = S1 + 0000
	state.r[V0] = state.r[S1] + 0x0000;


_0400173C:	// 400173c: <0d000470>	JAL	    040011c0
	state.r[V1] = 0 + 0x001F;
	sp_reg_pc = 0x0400173C;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _040011C0;


_04001740:	// 4001740: <2003001f>	ADDI      V1 = R0 + 001f
	state.r[V1] = 0 + 0x001F;


_04001744:	// 4001744: <40053000>	MFC0      A2 = SP DMA full
	state.r[A1] = 0;


_04001748:	// 4001748: <14a0fffe>	BNE       (R0!=A1) --> 1744
	sp_reg_pc = 0x04001748;
	if (state.r[A1] != 0)
	{
		goto _04001744;
	}


_0400174C:	// 400174c: <00000000>	NOP       


_04001750:	// 4001750: <09000446>	J         04001118
	state.r[S6] = (0 & 0);
	goto _04001118;


_04001754:	// 4001754: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_04001758:	// 4001758: <c81f2000>	LQV       vec31 <00> = [R0 + 0x00]
	{
		_u32 addr = (0x00000000 + 0);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[31].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[31].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[31].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[31].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[31].U64[0] = state.v[31].U64[0] & ~temp1;
			state.v[31].U64[1] = state.v[31].U64[1] & ~temp2;
			state.v[31].U64[0] = state.v[31].U64[0] | value1;
			state.v[31].U64[1] = state.v[31].U64[1] | value2;
		}
	}


_0400175C:	// 400175c: <4a1ce72c>	VXOR      vec28 = vec28 xor vec28[<none>]
	rsp_cop2_vxor(&state.v[28], &state.v[28], &state.v[28]);


_04001760:	// 4001760: <97150000>	LHU       S5 = [T8+0000]
	state.r[S5] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000000) & 0xfff);


_04001764:	// 4001764: <4a118c6c>	VXOR      vec17 = vec17 xor vec17[<none>]
	rsp_cop2_vxor(&state.v[17], &state.v[17], &state.v[17]);


_04001768:	// 4001768: <97140002>	LHU       S4 = [T8+0002]
	state.r[S4] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000002) & 0xfff);


_0400176C:	// 400176c: <4a1294ac>	VXOR      vec18 = vec18 xor vec18[<none>]
	rsp_cop2_vxor(&state.v[18], &state.v[18], &state.v[18]);


_04001770:	// 4001770: <97130004>	LHU       S3 = [T8+0004]
	state.r[S3] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_04001774:	// 4001774: <4a139cec>	VXOR      vec19 = vec19 xor vec19[<none>]
	rsp_cop2_vxor(&state.v[19], &state.v[19], &state.v[19]);


_04001778:	// 4001778: <12600054>	BEQ       (R0==S3) --> 18cc
	sp_reg_pc = 0x04001778;
	if (state.r[S3] == 0)
	{
		state.r[T6] = (state.r[K0] & 0x0000FFFF);
		goto _040018CC;
	}


_0400177C:	// 400177c: <334effff>	ANDI      T6 = K0 & ffff
	state.r[T6] = (state.r[K0] & 0x0000FFFF);


_04001780:	// 4001780: <488efd00>	MTC2      vec31 <10> = T6
	state.v[31].U16[2] = (_u16)state.r[T6];


_04001784:	// 4001784: <000e7080>	SLL       T6 = T6 << 2
	state.r[T6] = ((_u32)state.r[T6] << 2);


_04001788:	// 4001788: <488e8000>	MTC2      vec16 <00> = T6
	state.v[16].U16[7] = (_u16)state.r[T6];


_0400178C:	// 400178c: <3c0100ff>	LUI       AT = 0x00ff0000
	state.r[AT] = 0x00FF0000;


_04001790:	// 4001790: <4a14a52c>	VXOR      vec20 = vec20 xor vec20[<none>]
	rsp_cop2_vxor(&state.v[20], &state.v[20], &state.v[20]);


_04001794:	// 4001794: <3421ffff>	ORI       AT = AT | 0xffff
	state.r[AT] = (state.r[AT] | 0x0000FFFF);


_04001798:	// 4001798: <4a15ad6c>	VXOR      vec21 = vec21 xor vec21[<none>]
	rsp_cop2_vxor(&state.v[21], &state.v[21], &state.v[21]);


_0400179C:	// 400179c: <03219024>	AND       S2 = T9 & AT
	state.r[S2] = (state.r[T9] & state.r[AT]);


_040017A0:	// 40017a0: <4a16b5ac>	VXOR      vec22 = vec22 xor vec22[<none>]
	rsp_cop2_vxor(&state.v[22], &state.v[22], &state.v[22]);


_040017A4:	// 40017a4: <00191602>	SRL       V0 = T9 >> 24
	state.r[V0] = ((_u32)state.r[T9] >> 24);


_040017A8:	// 40017a8: <4a17bdec>	VXOR      vec23 = vec23 xor vec23[<none>]
	rsp_cop2_vxor(&state.v[23], &state.v[23], &state.v[23]);


_040017AC:	// 40017ac: <00021080>	SLL       V0 = V0 << 2
	state.r[V0] = ((_u32)state.r[V0] << 2);


_040017B0:	// 40017b0: <8c430320>	LW        V1 = [V0+0320]
	state.r[V1] = (_s32)Load32_DMEM((state.r[V0] + 0x00000320) & 0xfff);


_040017B4:	// 40017b4: <02439020>	ADD       S2 = S2+V1
	state.r[S2] = (state.r[S2] + state.r[V1]);


_040017B8:	// 40017b8: <eafc1000>	SLV       [S7 + 0x00] = vec28 <00>
	Save32_DMEM (state.v[28].U32[3], 0x00000000 + state.r[S7]);


_040017BC:	// 40017bc: <001a0c02>	SRL       AT = K0 >> 16
	state.r[AT] = ((_u32)state.r[K0] >> 16);


_040017C0:	// 40017c0: <30210001>	ANDI      AT = AT & 0001
	state.r[AT] = (state.r[AT] & 0x00000001);


_040017C4:	// 40017c4: <1c200009>	BGTZ      (R0>0) --> 17ec
	sp_reg_pc = 0x040017C4;
	if((_s32)state.r[AT] > 0)
	{
		goto _040017EC;
	}


_040017C8:	// 40017c8: <00000000>	NOP       


_040017CC:	// 40017cc: <22e10000>	ADDI      AT = S7 + 0000
	state.r[AT] = state.r[S7] + 0x0000;


_040017D0:	// 40017d0: <22420000>	ADDI      V0 = S2 + 0000
	state.r[V0] = state.r[S2] + 0x0000;


_040017D4:	// 40017d4: <0d000465>	JAL	    04001194
	state.r[V1] = 0 + 0x0007;
	sp_reg_pc = 0x040017D4;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_040017D8:	// 40017d8: <20030007>	ADDI      V1 = R0 + 0007
	state.r[V1] = 0 + 0x0007;


_040017DC:	// 40017dc: <40053000>	MFC0      A2 = SP DMA full
	state.r[A1] = 0;


_040017E0:	// 40017e0: <14a0fffe>	BNE       (R0!=A1) --> 17dc
	sp_reg_pc = 0x040017E0;
	if (state.r[A1] != 0)
	{
		goto _040017DC;
	}


_040017E4:	// 40017e4: <00000000>	NOP       


_040017E8:	// 40017e8: <0000b020>	ADD       S6 = R0+R0
	state.r[S6] = (0 + 0);


_040017EC:	// 40017ec: <12c00005>	BEQ       (R0==S6) --> 1804
	sp_reg_pc = 0x040017EC;
	if (state.r[S6] == 0)
	{
		goto _04001804;
	}


_040017F0:	// 40017f0: <00000000>	NOP       


_040017F4:	// 40017f4: <40013000>	MFC0      A2 = SP DRAM DMA address
	state.r[AT] = 0;


_040017F8:	// 40017f8: <1420fffe>	BNE       (R0!=AT) --> 17f4
	sp_reg_pc = 0x040017F8;
	if (state.r[AT] != 0)
	{
		goto _040017F4;
	}


_040017FC:	// 40017fc: <00000000>	NOP       


_04001800:	// 4001800: <0000b020>	ADD       S6 = R0+R0
	state.r[S6] = (0 + 0);


_04001804:	// 4001804: <200d04c0>	ADDI      T5 = R0 + 04c0
	state.r[T5] = 0 + 0x04C0;


_04001808:	// 4001808: <20010004>	ADDI      AT = R0 + 0004
	state.r[AT] = 0 + 0x0004;


_0400180C:	// 400180c: <48817000>	MTC2      vec14 <00> = AT
	state.v[14].U16[7] = (_u16)state.r[AT];


_04001810:	// 4001810: <c9b82001>	LQV       vec24 <00> = [T5 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[T5]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
			state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
			state.v[24].U64[0] = state.v[24].U64[0] | value1;
			state.v[24].U64[1] = state.v[24].U64[1] | value2;
		}
	}


_04001814:	// 4001814: <4b10c405>	VMUDM     vec16 = ( acc = vec24 * vec16[0] ) >> 16
	{
		_u16		s2value = state.v[16].U16[7];
		VMUDM_operation(0, state.v[16].U16[0], state.v[24].U16[0], s2value, 1, 0, 0, 1)
		VMUDM_operation(1, state.v[16].U16[1], state.v[24].U16[1], s2value, 1, 0, 0, 1)
		VMUDM_operation(2, state.v[16].U16[2], state.v[24].U16[2], s2value, 1, 0, 0, 1)
		VMUDM_operation(3, state.v[16].U16[3], state.v[24].U16[3], s2value, 1, 0, 0, 1)
		VMUDM_operation(4, state.v[16].U16[4], state.v[24].U16[4], s2value, 1, 0, 0, 1)
		VMUDM_operation(5, state.v[16].U16[5], state.v[24].U16[5], s2value, 1, 0, 0, 1)
		VMUDM_operation(6, state.v[16].U16[6], state.v[24].U16[6], s2value, 1, 0, 0, 1)
		VMUDM_operation(7, state.v[16].U16[7], state.v[24].U16[7], s2value, 1, 0, 0, 1)
	}


_04001818:	// 4001818: <cafc1c00>	LDV       vec28 <08> = [S7 + 0x00]
	rsp_ldv_compiler((state.r[S7] & 0xFFF), 28, 0);


_0400181C:	// 400181c: <e9b02001>	SQV       [T5 + 0x10] = vec16 <00>
	{
		_u32    addr = (0x00000010 + state.r[T5]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[16].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[16].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[16].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[16].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[16].U64[0] & temp1);
			value2 |= (state.v[16].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001820:	// 4001820: <c9b92000>	LQV       vec25 <00> = [T5 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[T5]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[25].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[25].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[25].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[25].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[25].U64[0] = state.v[25].U64[0] & ~temp1;
			state.v[25].U64[1] = state.v[25].U64[1] & ~temp2;
			state.v[25].U64[0] = state.v[25].U64[0] | value1;
			state.v[25].U64[1] = state.v[25].U64[1] | value2;
		}
	}


_04001824:	// 4001824: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001828:	// 4001828: <c9b72802>	LRV       vec23 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[23].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_0400182C:	// 400182c: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001830:	// 4001830: <c9b62802>	LRV       vec22 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[22].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_04001834:	// 4001834: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001838:	// 4001838: <c9b52802>	LRV       vec21 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[21].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_0400183C:	// 400183c: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001840:	// 4001840: <c9b42802>	LRV       vec20 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[20].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_04001844:	// 4001844: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001848:	// 4001848: <c9b32802>	LRV       vec19 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[19].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_0400184C:	// 400184c: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001850:	// 4001850: <c9b22802>	LRV       vec18 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[18].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_04001854:	// 4001854: <21adfffe>	ADDI      T5 = T5 + fffe
	state.r[T5] = state.r[T5] + 0xFFFFFFFE;


_04001858:	// 4001858: <c9b12802>	LRV       vec17 <00> = [T5 + 0x20]
	{
		_s32		addr;
		_s32		offset;
		_u32		i, length;

		addr = (0x00000020 + state.r[T5]);
		offset = (addr & 0xf) - 1;
		length = (addr & 0xf);
		addr &= 0xff0;
		for (i=0; i<length; i++) {
			state.v[17].U8[offset - i] = pDMEM[(addr ^ 3)];
			addr++;
		}
	}


_0400185C:	// 400185c: <cabe1800>	LDV       vec30 <00> = [S5 + 0x00]
	rsp_ldv_compiler((state.r[S5] & 0xFFF), 30, 8);


_04001860:	// 4001860: <cabe1c01>	LDV       vec30 <08> = [S5 + 0x08]
	rsp_ldv_compiler((state.r[S5] + 0x00000008) & 0xFFF, 30, 0);


_04001864:	// 4001864: <4bdccc07>	VMUDH     vec16 = ( acc = (vec25 * vec28[6]) << 16) >> 16

	// [start function: DKR1864_18B0]

	DKR1864_18B0();
	goto _040018B4;

_04001868:	// 4001868: <22b50010>	ADDI      S5 = S5 + 0010

_0400186C:	// 400186c: <4bfcc40f>	VMADH     vec16 = ( acc+= (vec24 * vec28[7]) << 16) >> 16

_04001870:	// 4001870: <2273fff0>	ADDI      S3 = S3 + fff0

_04001874:	// 4001874: <4b1ebc0f>	VMADH     vec16 = ( acc+= (vec23 * vec30[0]) << 16) >> 16

_04001878:	// 4001878: <4b3eb40f>	VMADH     vec16 = ( acc+= (vec22 * vec30[1]) << 16) >> 16

_0400187C:	// 400187c: <4b5eac0f>	VMADH     vec16 = ( acc+= (vec21 * vec30[2]) << 16) >> 16

_04001880:	// 4001880: <4b7ea40f>	VMADH     vec16 = ( acc+= (vec20 * vec30[3]) << 16) >> 16

_04001884:	// 4001884: <4b9e9f0f>	VMADH     vec28 = ( acc+= (vec19 * vec30[4]) << 16) >> 16

_04001888:	// 4001888: <4bbe940f>	VMADH     vec16 = ( acc+= (vec18 * vec30[5]) << 16) >> 16

_0400188C:	// 400188c: <4bde8c0f>	VMADH     vec16 = ( acc+= (vec17 * vec30[6]) << 16) >> 16

_04001890:	// 4001890: <4bbff40f>	VMADH     vec16 = ( acc+= (vec30 * vec31[5]) << 16) >> 16

_04001894:	// 4001894: <cabe1800>	LDV       vec30 <00> = [S5 + 0x00]

_04001898:	// 4001898: <4b3c7e9d>	VSAW $v26, $v15, $v28[[1]]

_0400189C:	// 400189c: <cabe1c01>	LDV       vec30 <08> = [S5 + 0x08]

_040018A0:	// 40018a0: <4b1c7f1d>	VSAW $v28, $v15, $v28[[0]]

_040018A4:	// 40018a4: <4b0ed406>	VMUDN     vec16 = ( acc = vec26 * vec14[0]      ) >> 16

_040018A8:	// 40018a8: <4b0ee70f>	VMADH     vec28 = ( acc+= (vec28 * vec14[0]) << 16) >> 16

_040018AC:	// 40018ac: <ea9c1800>	SDV       [S4 + 0x00] = vec28 <00>

_040018B0:	// 40018b0: <ea9c1c01>	SDV       [S4 + 0x04] = vec28 <08>
	ErrorToCallFunction(0x040018B0);

	// [end of function: DKR1864_18B0]

_040018B4:	// 40018b4: <1e60ffeb>	BGTZ      (R0>0) --> 1864
	sp_reg_pc = 0x040018B4;
	if((_s32)state.r[S3] > 0)
	{
		state.r[S4] = state.r[S4] + 0x0010;
		goto _04001864;
	}


_040018B8:	// 40018b8: <22940010>	ADDI      S4 = S4 + 0010
	state.r[S4] = state.r[S4] + 0x0010;


_040018BC:	// 40018bc: <2281fff8>	ADDI      AT = S4 + fff8
	state.r[AT] = state.r[S4] + 0xFFFFFFF8;


_040018C0:	// 40018c0: <22420000>	ADDI      V0 = S2 + 0000
	state.r[V0] = state.r[S2] + 0x0000;


_040018C4:	// 40018c4: <0d000470>	JAL	    040011c0
	state.r[V1] = 0 + 0x0007;
	sp_reg_pc = 0x040018C4;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _040011C0;


_040018C8:	// 40018c8: <20030007>	ADDI      V1 = R0 + 0007
	state.r[V1] = 0 + 0x0007;


_040018CC:	// 40018cc: <09000446>	J         04001118
	goto _04001118;


_040018D0:	// 40018d0: <00000000>	NOP       


_040018D4:	// 40018d4: <87080000>	LH        T0 = [T8+0000]
	state.r[T0] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000000) & 0xfff);


_040018D8:	// 40018d8: <87130002>	LH        S3 = [T8+0002]
	state.r[S3] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000002) & 0xfff);


_040018DC:	// 40018dc: <87120004>	LH        S2 = [T8+0004]
	state.r[S2] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_040018E0:	// 40018e0: <3c0400ff>	LUI       A0 = 0x00ff0000
	state.r[A0] = 0x00FF0000;


_040018E4:	// 40018e4: <3484ffff>	ORI       A0 = A0 | 0xffff
	state.r[A0] = (state.r[A0] | 0x0000FFFF);


_040018E8:	// 40018e8: <03241024>	AND       V0 = T9 & A0
	state.r[V0] = (state.r[T9] & state.r[A0]);


_040018EC:	// 40018ec: <00192e02>	SRL       A1 = T9 >> 24
	state.r[A1] = ((_u32)state.r[T9] >> 24);


_040018F0:	// 40018f0: <00052880>	SLL       A1 = A1 << 2
	state.r[A1] = ((_u32)state.r[A1] << 2);


_040018F4:	// 40018f4: <8ca60320>	LW        A2 = [A1+0320]
	state.r[A2] = (_s32)Load32_DMEM((state.r[A1] + 0x00000320) & 0xfff);


_040018F8:	// 40018f8: <00461020>	ADD       V0 = V0+A2
	state.r[V0] = (state.r[V0] + state.r[A2]);


_040018FC:	// 40018fc: <22e10000>	ADDI      AT = S7 + 0000
	state.r[AT] = state.r[S7] + 0x0000;


_04001900:	// 4001900: <aee20040>	SW        [S7+0040] = V0
	Save32_DMEM((_u32)state.r[V0], (state.r[S7] + 0x00000040) & 0xfff);


_04001904:	// 4001904: <2003001f>	ADDI      V1 = R0 + 001f
	state.r[V1] = 0 + 0x001F;


_04001908:	// 4001908: <001a3c02>	SRL       A3 = K0 >> 16
	state.r[A3] = ((_u32)state.r[K0] >> 16);


_0400190C:	// 400190c: <30ea0001>	ANDI      T2 = A3 & 0001
	state.r[T2] = (state.r[A3] & 0x00000001);


_04001910:	// 4001910: <1d400009>	BGTZ      (R0>0) --> 1938
	sp_reg_pc = 0x04001910;
	if((_s32)state.r[T2] > 0)
	{
		goto _04001938;
	}


_04001914:	// 4001914: <00000000>	NOP       


_04001918:	// 4001918: <0d000465>	JAL	    04001194
	state.r[T2] = (0 + state.r[A3]);
	sp_reg_pc = 0x04001918;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_0400191C:	// 400191c: <00075020>	ADD       T2 = R0+A3
	state.r[T2] = (0 + state.r[A3]);


_04001920:	// 4001920: <000a3820>	ADD       A3 = R0+T2
	state.r[A3] = (0 + state.r[T2]);


_04001924:	// 4001924: <40013000>	MFC0      A2 = SP DRAM DMA address
	state.r[AT] = 0;


_04001928:	// 4001928: <1420fffe>	BNE       (R0!=AT) --> 1924
	sp_reg_pc = 0x04001928;
	if (state.r[AT] != 0)
	{
		goto _04001924;
	}


_0400192C:	// 400192c: <00000000>	NOP       


_04001930:	// 4001930: <09000657>	J         0400195c
	state.r[S6] = (0 + 0);
	goto _0400195C;


_04001934:	// 4001934: <0000b020>	ADD       S6 = R0+R0
	state.r[S6] = (0 + 0);


_04001938:	// 4001938: <12c00005>	BEQ       (R0==S6) --> 1950
	sp_reg_pc = 0x04001938;
	if (state.r[S6] == 0)
	{
		goto _04001950;
	}


_0400193C:	// 400193c: <00000000>	NOP       


_04001940:	// 4001940: <400a3000>	MFC0      A2 = DP CMD DMA current
	state.r[T2] = 0;


_04001944:	// 4001944: <1540fffe>	BNE       (R0!=T2) --> 1940
	sp_reg_pc = 0x04001944;
	if (state.r[T2] != 0)
	{
		goto _04001940;
	}


_04001948:	// 4001948: <00000000>	NOP       


_0400194C:	// 400194c: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_04001950:	// 4001950: <a6e00008>	SH        [S7+0008] = R0
	Save16_DMEM((_u16)0, (state.r[S7] + 0x00000008) & 0xfff);


_04001954:	// 4001954: <4a10842c>	VXOR      vec16 = vec16 xor vec16[<none>]
	rsp_cop2_vxor(&state.v[16], &state.v[16], &state.v[16]);


_04001958:	// 4001958: <eaf01800>	SDV       [S7 + 0x00] = vec16 <00>
	{
		_u32	addr = (0x00000000 + state.r[S7]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[16].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[16].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[16].U32[0x00000003];
		}
	}


_0400195C:	// 400195c: <30ea0002>	ANDI      T2 = A3 & 0002
	state.r[T2] = (state.r[A3] & 0x00000002);


_04001960:	// 4001960: <11400006>	BEQ       (R0==T2) --> 197c
	sp_reg_pc = 0x04001960;
	if (state.r[T2] == 0)
	{
		goto _0400197C;
	}


_04001964:	// 4001964: <00000000>	NOP       


_04001968:	// 4001968: <86eb000a>	LH        T3 = [S7+000a]
	state.r[T3] = (_s32)(_s16)Load16_DMEM((state.r[S7] + 0x0000000A) & 0xfff);


_0400196C:	// 400196c: <cae32001>	LQV       vec03 <00> = [S7 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[S7]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[3].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[3].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[3].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[3].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[3].U64[0] = state.v[3].U64[0] & ~temp1;
			state.v[3].U64[1] = state.v[3].U64[1] & ~temp2;
			state.v[3].U64[0] = state.v[3].U64[0] | value1;
			state.v[3].U64[1] = state.v[3].U64[1] | value2;
		}
	}


_04001970:	// 4001970: <e903187e>	SDV       [T0 + 0x38] = vec03 <00>
	{
		_u32	addr = (0xFFFFFFF0 + state.r[T0]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[3].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[3].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[3].U32[0x00000003];
		}
	}


_04001974:	// 4001974: <e9031c7f>	SDV       [T0 + 0x3c] = vec03 <08>
	{
		_u32	addr = (0xFFFFFFF8 + state.r[T0]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[3].U64[0x00000000], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[3].U32[0x00000000];
			*(_u32 *)&pDMEM[addr  ] = state.v[3].U32[0x00000001];
		}
	}


_04001978:	// 4001978: <010b4022>	SUB       T0 = T0-T3
	state.r[T0] = (state.r[T0] - state.r[T3]);


_0400197C:	// 400197c: <2108fff8>	ADDI      T0 = T0 + fff8
	state.r[T0] = state.r[T0] + 0xFFFFFFF8;


_04001980:	// 4001980: <caf70f04>	LSV       vec23 <14> = [S7 + 0x08]
	state.v[23].U16[0] = Load16_DMEM(0x00000008 + state.r[S7]);


_04001984:	// 4001984: <caf01800>	LDV       vec16 <00> = [S7 + 0x00]
	rsp_ldv_compiler((state.r[S7] & 0xFFF), 16, 8);


_04001988:	// 4001988: <e9101800>	SDV       [T0 + 0x00] = vec16 <00>
	{
		_u32	addr = (0x00000000 + state.r[T0]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[16].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[16].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[16].U32[0x00000003];
		}
	}


_0400198C:	// 400198c: <48889200>	MTC2      vec18 <04> = T0
	state.v[18].U16[5] = (_u16)state.r[T0];


_04001990:	// 4001990: <200a00d0>	ADDI      T2 = R0 + 00d0
	state.r[T2] = 0 + 0x00D0;


_04001994:	// 4001994: <488a9300>	MTC2      vec18 <06> = T2
	state.v[18].U16[4] = (_u16)state.r[T2];


_04001998:	// 4001998: <489a9400>	MTC2      vec18 <08> = K0
	state.v[18].U16[3] = (_u16)state.r[K0];


_0400199C:	// 400199c: <200a0040>	ADDI      T2 = R0 + 0040
	state.r[T2] = 0 + 0x0040;


_040019A0:	// 40019a0: <488a9500>	MTC2      vec18 <10> = T2
	state.v[18].U16[2] = (_u16)state.r[T2];


_040019A4:	// 40019a4: <20090050>	ADDI      T1 = R0 + 0050
	state.r[T1] = 0 + 0x0050;


_040019A8:	// 40019a8: <c93f2001>	LQV       vec31 <00> = [T1 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[31].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[31].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[31].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[31].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[31].U64[0] = state.v[31].U64[0] & ~temp1;
			state.v[31].U64[1] = state.v[31].U64[1] & ~temp2;
			state.v[31].U64[0] = state.v[31].U64[0] | value1;
			state.v[31].U64[1] = state.v[31].U64[1] | value2;
		}
	}


_040019AC:	// 40019ac: <c9392000>	LQV       vec25 <00> = [T1 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[25].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[25].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[25].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[25].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[25].U64[0] = state.v[25].U64[0] & ~temp1;
			state.v[25].U64[1] = state.v[25].U64[1] & ~temp2;
			state.v[25].U64[0] = state.v[25].U64[0] | value1;
			state.v[25].U64[1] = state.v[25].U64[1] | value2;
		}
	}


_040019B0:	// 40019b0: <4a1fce51>	VSUB      vec25 = vec25 - vec31[<none>]
	{
		_u16		flag0 = state.flag[0];
		VSUB_operation(0, state.v[25].U16[0], state.v[25].U16[0], state.v[31].U16[0], 1, 0, 0, 1)
		VSUB_operation(1, state.v[25].U16[1], state.v[25].U16[1], state.v[31].U16[1], 1, 0, 0, 1)
		VSUB_operation(2, state.v[25].U16[2], state.v[25].U16[2], state.v[31].U16[2], 1, 0, 0, 1)
		VSUB_operation(3, state.v[25].U16[3], state.v[25].U16[3], state.v[31].U16[3], 1, 0, 0, 1)
		VSUB_operation(4, state.v[25].U16[4], state.v[25].U16[4], state.v[31].U16[4], 1, 0, 0, 1)
		VSUB_operation(5, state.v[25].U16[5], state.v[25].U16[5], state.v[31].U16[5], 1, 0, 0, 1)
		VSUB_operation(6, state.v[25].U16[6], state.v[25].U16[6], state.v[31].U16[6], 1, 0, 0, 1)
		VSUB_operation(7, state.v[25].U16[7], state.v[25].U16[7], state.v[31].U16[7], 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


_040019B4:	// 40019b4: <c93e2002>	LQV       vec30 <00> = [T1 + 0x20]
	{
		_u32 addr = (0x00000020 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[30].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[30].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[30].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[30].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[30].U64[0] = state.v[30].U64[0] & ~temp1;
			state.v[30].U64[1] = state.v[30].U64[1] & ~temp2;
			state.v[30].U64[0] = state.v[30].U64[0] | value1;
			state.v[30].U64[1] = state.v[30].U64[1] | value2;
		}
	}


_040019B8:	// 40019b8: <c93d2003>	LQV       vec29 <00> = [T1 + 0x30]
	{
		_u32 addr = (0x00000030 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[29].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[29].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[29].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[29].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[29].U64[0] = state.v[29].U64[0] & ~temp1;
			state.v[29].U64[1] = state.v[29].U64[1] & ~temp2;
			state.v[29].U64[0] = state.v[29].U64[0] | value1;
			state.v[29].U64[1] = state.v[29].U64[1] | value2;
		}
	}


_040019BC:	// 40019bc: <c93c2004>	LQV       vec28 <00> = [T1 + 0x40]
	{
		_u32 addr = (0x00000040 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[28].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[28].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[28].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[28].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[28].U64[0] = state.v[28].U64[0] & ~temp1;
			state.v[28].U64[1] = state.v[28].U64[1] & ~temp2;
			state.v[28].U64[0] = state.v[28].U64[0] | value1;
			state.v[28].U64[1] = state.v[28].U64[1] | value2;
		}
	}


_040019C0:	// 40019c0: <c93b2005>	LQV       vec27 <00> = [T1 + 0x50]
	{
		_u32 addr = (0x00000050 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}


_040019C4:	// 40019c4: <c93a2006>	LQV       vec26 <00> = [T1 + 0x60]
	{
		_u32 addr = (0x00000060 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[26].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[26].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[26].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[26].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[26].U64[0] = state.v[26].U64[0] & ~temp1;
			state.v[26].U64[1] = state.v[26].U64[1] & ~temp2;
			state.v[26].U64[0] = state.v[26].U64[0] | value1;
			state.v[26].U64[1] = state.v[26].U64[1] | value2;
		}
	}


_040019C8:	// 40019c8: <4a1fce51>	VSUB      vec25 = vec25 - vec31[<none>]
	{
		_u16		flag0 = state.flag[0];
		VSUB_operation(0, state.v[25].U16[0], state.v[25].U16[0], state.v[31].U16[0], 1, 0, 0, 1)
		VSUB_operation(1, state.v[25].U16[1], state.v[25].U16[1], state.v[31].U16[1], 1, 0, 0, 1)
		VSUB_operation(2, state.v[25].U16[2], state.v[25].U16[2], state.v[31].U16[2], 1, 0, 0, 1)
		VSUB_operation(3, state.v[25].U16[3], state.v[25].U16[3], state.v[31].U16[3], 1, 0, 0, 1)
		VSUB_operation(4, state.v[25].U16[4], state.v[25].U16[4], state.v[31].U16[4], 1, 0, 0, 1)
		VSUB_operation(5, state.v[25].U16[5], state.v[25].U16[5], state.v[31].U16[5], 1, 0, 0, 1)
		VSUB_operation(6, state.v[25].U16[6], state.v[25].U16[6], state.v[31].U16[6], 1, 0, 0, 1)
		VSUB_operation(7, state.v[25].U16[7], state.v[25].U16[7], state.v[31].U16[7], 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


_040019CC:	// 40019cc: <c9382007>	LQV       vec24 <00> = [T1 + 0x70]
	{
		_u32 addr = (0x00000070 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
			state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
			state.v[24].U64[0] = state.v[24].U64[0] | value1;
			state.v[24].U64[1] = state.v[24].U64[1] | value2;
		}
	}


_040019D0:	// 40019d0: <22f50020>	ADDI      S5 = S7 + 0020
	state.r[S5] = state.r[S7] + 0x0020;


_040019D4:	// 40019d4: <22f40030>	ADDI      S4 = S7 + 0030
	state.r[S4] = state.r[S7] + 0x0030;


_040019D8:	// 40019d8: <4a16b5ac>	VXOR      vec22 = vec22 xor vec22[<none>]
	rsp_cop2_vxor(&state.v[22], &state.v[22], &state.v[22]);


_040019DC:	// 40019dc: <4bf7fdc5>	VMUDM     vec23 = ( acc = vec31 * vec23[7] ) >> 16
	{
		_u16		s2value = state.v[23].U16[0];
		VMUDM_operation(0, state.v[23].U16[0], state.v[31].U16[0], s2value, 0, 1, 1, 1)
		VMUDM_operation(1, state.v[23].U16[1], state.v[31].U16[1], s2value, 0, 1, 1, 1)
		VMUDM_operation(2, state.v[23].U16[2], state.v[31].U16[2], s2value, 0, 1, 1, 1)
		VMUDM_operation(3, state.v[23].U16[3], state.v[31].U16[3], s2value, 0, 1, 1, 1)
		VMUDM_operation(4, state.v[23].U16[4], state.v[31].U16[4], s2value, 0, 1, 1, 1)
		VMUDM_operation(5, state.v[23].U16[5], state.v[31].U16[5], s2value, 0, 1, 1, 1)
		VMUDM_operation(6, state.v[23].U16[6], state.v[31].U16[6], s2value, 0, 1, 1, 1)
		VMUDM_operation(7, state.v[23].U16[7], state.v[31].U16[7], s2value, 0, 1, 1, 1)
	}


_040019E0:	// 40019e0: <4b92cd8d>	VMADM     vec22 = ( acc+= vec25 * vec18[4] ) >> 16
	{
		_u16		s2value = state.v[18].U16[3];
		VMADM_operation(0, state.v[22].U16[0], state.v[25].U16[0], s2value, 1, 1, 1, 1)
		VMADM_operation(1, state.v[22].U16[1], state.v[25].U16[1], s2value, 1, 1, 1, 1)
		VMADM_operation(2, state.v[22].U16[2], state.v[25].U16[2], s2value, 1, 1, 1, 1)
		VMADM_operation(3, state.v[22].U16[3], state.v[25].U16[3], s2value, 1, 1, 1, 1)
		VMADM_operation(4, state.v[22].U16[4], state.v[25].U16[4], s2value, 1, 1, 1, 1)
		VMADM_operation(5, state.v[22].U16[5], state.v[25].U16[5], s2value, 1, 1, 1, 1)
		VMADM_operation(6, state.v[22].U16[6], state.v[25].U16[6], s2value, 1, 1, 1, 1)
		VMADM_operation(7, state.v[22].U16[7], state.v[25].U16[7], s2value, 1, 1, 1, 1)
	}


_040019E4:	// 40019e4: <4b1efdce>	VMADN     vec23 = ( acc+= vec31 * vec30[0] )
	{
		_u16		s2value = state.v[30].U16[7];
		VMADN_operation(0, state.v[23].U16[0], state.v[31].U16[0], s2value, 1, 0, 0, 1)
		VMADN_operation(1, state.v[23].U16[1], state.v[31].U16[1], s2value, 1, 0, 0, 1)
		VMADN_operation(2, state.v[23].U16[2], state.v[31].U16[2], s2value, 1, 0, 0, 1)
		VMADN_operation(3, state.v[23].U16[3], state.v[31].U16[3], s2value, 1, 0, 0, 1)
		VMADN_operation(4, state.v[23].U16[4], state.v[31].U16[4], s2value, 1, 0, 0, 1)
		VMADN_operation(5, state.v[23].U16[5], state.v[31].U16[5], s2value, 1, 0, 0, 1)
		VMADN_operation(6, state.v[23].U16[6], state.v[31].U16[6], s2value, 1, 0, 0, 1)
		VMADN_operation(7, state.v[23].U16[7], state.v[31].U16[7], s2value, 1, 0, 0, 1)
	}


_040019E8:	// 40019e8: <4b52fd46>	VMUDN     vec21 = ( acc = vec31 * vec18[2]      ) >> 16
	{
		_u16		s2value = state.v[18].U16[5];
		VMUDN_operation(0, state.v[21].U16[0], state.v[31].U16[0], s2value, 0, 1, 1, 1)
		VMUDN_operation(1, state.v[21].U16[1], state.v[31].U16[1], s2value, 0, 1, 1, 1)
		VMUDN_operation(2, state.v[21].U16[2], state.v[31].U16[2], s2value, 0, 1, 1, 1)
		VMUDN_operation(3, state.v[21].U16[3], state.v[31].U16[3], s2value, 0, 1, 1, 1)
		VMUDN_operation(4, state.v[21].U16[4], state.v[31].U16[4], s2value, 0, 1, 1, 1)
		VMUDN_operation(5, state.v[21].U16[5], state.v[31].U16[5], s2value, 0, 1, 1, 1)
		VMUDN_operation(6, state.v[21].U16[6], state.v[31].U16[6], s2value, 0, 1, 1, 1)
		VMUDN_operation(7, state.v[21].U16[7], state.v[31].U16[7], s2value, 0, 1, 1, 1)
	}


_040019EC:	// 40019ec: <4b5eb54e>	VMADN     vec21 = ( acc+= vec22 * vec30[2] )
	{
		_u16		s2value = state.v[30].U16[5];
		VMADN_operation(0, state.v[21].U16[0], state.v[22].U16[0], s2value, 1, 0, 0, 1)
		VMADN_operation(1, state.v[21].U16[1], state.v[22].U16[1], s2value, 1, 0, 0, 1)
		VMADN_operation(2, state.v[21].U16[2], state.v[22].U16[2], s2value, 1, 0, 0, 1)
		VMADN_operation(3, state.v[21].U16[3], state.v[22].U16[3], s2value, 1, 0, 0, 1)
		VMADN_operation(4, state.v[21].U16[4], state.v[22].U16[4], s2value, 1, 0, 0, 1)
		VMADN_operation(5, state.v[21].U16[5], state.v[22].U16[5], s2value, 1, 0, 0, 1)
		VMADN_operation(6, state.v[21].U16[6], state.v[22].U16[6], s2value, 1, 0, 0, 1)
		VMADN_operation(7, state.v[21].U16[7], state.v[22].U16[7], s2value, 1, 0, 0, 1)
	}


_040019F0:	// 40019f0: <4bb2bc44>	VMUDL     vec17 = ( acc = (vec23 * vec18[5] >> 16)      )
	{
		_u16		s2value = state.v[18].U16[2];
		VMUDL_operation(0, state.v[17].U16[0], state.v[23].U16[0], s2value, 1, 0, 0, 1)
		VMUDL_operation(1, state.v[17].U16[1], state.v[23].U16[1], s2value, 1, 0, 0, 1)
		VMUDL_operation(2, state.v[17].U16[2], state.v[23].U16[2], s2value, 1, 0, 0, 1)
		VMUDL_operation(3, state.v[17].U16[3], state.v[23].U16[3], s2value, 1, 0, 0, 1)
		VMUDL_operation(4, state.v[17].U16[4], state.v[23].U16[4], s2value, 1, 0, 0, 1)
		VMUDL_operation(5, state.v[17].U16[5], state.v[23].U16[5], s2value, 1, 0, 0, 1)
		VMUDL_operation(6, state.v[17].U16[6], state.v[23].U16[6], s2value, 1, 0, 0, 1)
		VMUDL_operation(7, state.v[17].U16[7], state.v[23].U16[7], s2value, 1, 0, 0, 1)
	}


_040019F4:	// 40019f4: <4b9e8c46>	VMUDN     vec17 = ( acc = vec17 * vec30[4]      ) >> 16
	{
		_u16		s2value = state.v[30].U16[3];
		VMUDN_operation(0, state.v[17].U16[0], state.v[17].U16[0], s2value, 0, 1, 1, 1)
		VMUDN_operation(1, state.v[17].U16[1], state.v[17].U16[1], s2value, 0, 1, 1, 1)
		VMUDN_operation(2, state.v[17].U16[2], state.v[17].U16[2], s2value, 0, 1, 1, 1)
		VMUDN_operation(3, state.v[17].U16[3], state.v[17].U16[3], s2value, 0, 1, 1, 1)
		VMUDN_operation(4, state.v[17].U16[4], state.v[17].U16[4], s2value, 0, 1, 1, 1)
		VMUDN_operation(5, state.v[17].U16[5], state.v[17].U16[5], s2value, 0, 1, 1, 1)
		VMUDN_operation(6, state.v[17].U16[6], state.v[17].U16[6], s2value, 0, 1, 1, 1)
		VMUDN_operation(7, state.v[17].U16[7], state.v[17].U16[7], s2value, 0, 1, 1, 1)
	}


_040019F8:	// 40019f8: <4b72fc4e>	VMADN     vec17 = ( acc+= vec31 * vec18[3] )
	{
		_u16		s2value = state.v[18].U16[4];
		VMADN_operation(0, state.v[17].U16[0], state.v[31].U16[0], s2value, 1, 0, 0, 1)
		VMADN_operation(1, state.v[17].U16[1], state.v[31].U16[1], s2value, 1, 0, 0, 1)
		VMADN_operation(2, state.v[17].U16[2], state.v[31].U16[2], s2value, 1, 0, 0, 1)
		VMADN_operation(3, state.v[17].U16[3], state.v[31].U16[3], s2value, 1, 0, 0, 1)
		VMADN_operation(4, state.v[17].U16[4], state.v[31].U16[4], s2value, 1, 0, 0, 1)
		VMADN_operation(5, state.v[17].U16[5], state.v[31].U16[5], s2value, 1, 0, 0, 1)
		VMADN_operation(6, state.v[17].U16[6], state.v[31].U16[6], s2value, 1, 0, 0, 1)
		VMADN_operation(7, state.v[17].U16[7], state.v[31].U16[7], s2value, 1, 0, 0, 1)
	}


_040019FC:	// 40019fc: <c9392000>	LQV       vec25 <00> = [T1 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[T1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[25].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[25].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[25].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[25].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[25].U64[0] = state.v[25].U64[0] & ~temp1;
			state.v[25].U64[1] = state.v[25].U64[1] & ~temp2;
			state.v[25].U64[0] = state.v[25].U64[0] | value1;
			state.v[25].U64[1] = state.v[25].U64[1] | value2;
		}
	}


_04001A00:	// 4001a00: <eab52000>	SQV       [S5 + 0x00] = vec21 <00>
	{
		_u32    addr = (0x00000000 + state.r[S5]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[21].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[21].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[21].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[21].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[21].U64[0] & temp1);
			value2 |= (state.v[21].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001A04:	// 4001a04: <ea912000>	SQV       [S4 + 0x00] = vec17 <00>
	{
		_u32    addr = (0x00000000 + state.r[S4]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[17].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[17].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[17].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[17].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[17].U64[0] & temp1);
			value2 |= (state.v[17].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001A08:	// 4001a08: <eaf70b84>	SSV       [S7 + 0x08] = vec23 <07>
	Save16_DMEM(state.v[23].U16[4], (0x00000008 + state.r[S7]) & 0xfff);


_04001A0C:	// 4001a0c: <86b10000>	LH        S1 = [S5+0000]
	state.r[S1] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x00000000) & 0xfff);


_04001A10:	// 4001a10: <86890000>	LH        T1 = [S4+0000]
	state.r[T1] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x00000000) & 0xfff);


_04001A14:	// 4001a14: <86ad0008>	LH        T5 = [S5+0008]
	state.r[T5] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x00000008) & 0xfff);


_04001A18:	// 4001a18: <86850008>	LH        A1 = [S4+0008]
	state.r[A1] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x00000008) & 0xfff);


_04001A1C:	// 4001a1c: <86b00002>	LH        S0 = [S5+0002]
	state.r[S0] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x00000002) & 0xfff);


_04001A20:	// 4001a20: <86880002>	LH        T0 = [S4+0002]
	state.r[T0] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x00000002) & 0xfff);


_04001A24:	// 4001a24: <86ac000a>	LH        T4 = [S5+000a]
	state.r[T4] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x0000000A) & 0xfff);


_04001A28:	// 4001a28: <8684000a>	LH        A0 = [S4+000a]
	state.r[A0] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x0000000A) & 0xfff);


_04001A2C:	// 4001a2c: <86af0004>	LH        T7 = [S5+0004]
	state.r[T7] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x00000004) & 0xfff);


_04001A30:	// 4001a30: <86870004>	LH        A3 = [S4+0004]
	state.r[A3] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x00000004) & 0xfff);


_04001A34:	// 4001a34: <86ab000c>	LH        T3 = [S5+000c]
	state.r[T3] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x0000000C) & 0xfff);


_04001A38:	// 4001a38: <8683000c>	LH        V1 = [S4+000c]
	state.r[V1] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x0000000C) & 0xfff);


_04001A3C:	// 4001a3c: <86ae0006>	LH        T6 = [S5+0006]
	state.r[T6] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x00000006) & 0xfff);


_04001A40:	// 4001a40: <86860006>	LH        A2 = [S4+0006]
	state.r[A2] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x00000006) & 0xfff);


_04001A44:	// 4001a44: <86aa000e>	LH        T2 = [S5+000e]
	state.r[T2] = (_s32)(_s16)Load16_DMEM((state.r[S5] + 0x0000000E) & 0xfff);


_04001A48:	// 4001a48: <8682000e>	LH        V0 = [S4+000e]
	state.r[V0] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x0000000E) & 0xfff);


_04001A4C:	// 4001a4c: <ca301800>	LDV       vec16 <00> = [S1 + 0x00]
	// In function: Mario19D8_1AC4
	//Call the function: Mario19D8_1AC4
	Mario19D8_1AC4();
	goto _04001B3C;

_04001A50:	// 4001a50: <4bf7fdc5>	VMUDM     vec23 = ( acc = vec31 * vec23[7] ) >> 16
	ErrorToCallFunction(0x04001A50);

_04001A54:	// 4001a54: <c92f1800>	LDV       vec15 <00> = [T1 + 0x00]
	ErrorToCallFunction(0x04001A54);

_04001A58:	// 4001a58: <4bf6fdcf>	VMADH     vec23 = ( acc+= (vec31 * vec22[7]) << 16) >> 16
	ErrorToCallFunction(0x04001A58);

_04001A5C:	// 4001a5c: <c9b01c00>	LDV       vec16 <08> = [T5 + 0x00]
	ErrorToCallFunction(0x04001A5C);

_04001A60:	// 4001a60: <4b92cd8d>	VMADM     vec22 = ( acc+= vec25 * vec18[4] ) >> 16
	ErrorToCallFunction(0x04001A60);

_04001A64:	// 4001a64: <c8af1c00>	LDV       vec15 <08> = [A1 + 0x00]
	ErrorToCallFunction(0x04001A64);

_04001A68:	// 4001a68: <4b1efdce>	VMADN     vec23 = ( acc+= vec31 * vec30[0] )
	ErrorToCallFunction(0x04001A68);

_04001A6C:	// 4001a6c: <ca0e1800>	LDV       vec14 <00> = [S0 + 0x00]
	ErrorToCallFunction(0x04001A6C);

_04001A70:	// 4001a70: <4b52fd46>	VMUDN     vec21 = ( acc = vec31 * vec18[2]      ) >> 16
	ErrorToCallFunction(0x04001A70);

_04001A74:	// 4001a74: <c90d1800>	LDV       vec13 <00> = [T0 + 0x00]
	ErrorToCallFunction(0x04001A74);

_04001A78:	// 4001a78: <4b5eb54e>	VMADN     vec21 = ( acc+= vec22 * vec30[2] )
	ErrorToCallFunction(0x04001A78);

_04001A7C:	// 4001a7c: <c98e1c00>	LDV       vec14 <08> = [T4 + 0x00]
	ErrorToCallFunction(0x04001A7C);

_04001A80:	// 4001a80: <4bb2bc44>	VMUDL     vec17 = ( acc = (vec23 * vec18[5] >> 16)      )
	ErrorToCallFunction(0x04001A80);

_04001A84:	// 4001a84: <c88d1c00>	LDV       vec13 <08> = [A0 + 0x00]
	ErrorToCallFunction(0x04001A84);

_04001A88:	// 4001a88: <c9ec1800>	LDV       vec12 <00> = [T7 + 0x00]
	ErrorToCallFunction(0x04001A88);

_04001A8C:	// 4001a8c: <c8eb1800>	LDV       vec11 <00> = [A3 + 0x00]
	ErrorToCallFunction(0x04001A8C);

_04001A90:	// 4001a90: <c96c1c00>	LDV       vec12 <08> = [T3 + 0x00]
	ErrorToCallFunction(0x04001A90);

_04001A94:	// 4001a94: <4b9e8c46>	VMUDN     vec17 = ( acc = vec17 * vec30[4]      ) >> 16
	ErrorToCallFunction(0x04001A94);

_04001A98:	// 4001a98: <c86b1c00>	LDV       vec11 <08> = [V1 + 0x00]
	ErrorToCallFunction(0x04001A98);

_04001A9C:	// 4001a9c: <c9ca1800>	LDV       vec10 <00> = [T6 + 0x00]
	ErrorToCallFunction(0x04001A9C);

_04001AA0:	// 4001aa0: <c8c91800>	LDV       vec09 <00> = [A2 + 0x00]
	ErrorToCallFunction(0x04001AA0);

_04001AA4:	// 4001aa4: <4b72fc4e>	VMADN     vec17 = ( acc+= vec31 * vec18[3] )
	ErrorToCallFunction(0x04001AA4);

_04001AA8:	// 4001aa8: <c94a1c00>	LDV       vec10 <08> = [T2 + 0x00]
	ErrorToCallFunction(0x04001AA8);

_04001AAC:	// 4001aac: <4a0f8200>	VMULF     vec08 = ( acc = (vec16 * vec15[<none>]) << 1 ) >> 16
	ErrorToCallFunction(0x04001AAC);

_04001AB0:	// 4001ab0: <c8491c00>	LDV       vec09 <08> = [V0 + 0x00]
	ErrorToCallFunction(0x04001AB0);

_04001AB4:	// 4001ab4: <4a0d71c0>	VMULF     vec07 = ( acc = (vec14 * vec13[<none>]) << 1 ) >> 16
	ErrorToCallFunction(0x04001AB4);

_04001AB8:	// 4001ab8: <eab52000>	SQV       [S5 + 0x00] = vec21 <00>
	ErrorToCallFunction(0x04001AB8);

_04001ABC:	// 4001abc: <4a0b6180>	VMULF     vec06 = ( acc = (vec12 * vec11[<none>]) << 1 ) >> 16
	ErrorToCallFunction(0x04001ABC);

_04001AC0:	// 4001ac0: <ea912000>	SQV       [S4 + 0x00] = vec17 <00>
	ErrorToCallFunction(0x04001AC0);

_04001AC4:	// 4001ac4: <86b10000>	LH        S1 = [S5+0000]
	ErrorToCallFunction(0x04001AC4);

_04001AC8:	// 4001ac8: <4a095140>	VMULF     vec05 = ( acc = (vec10 * vec09[<none>]) << 1 ) >> 16
	ErrorToCallFunction(0x04001AC8);

_04001ACC:	// 4001acc: <86890000>	LH        T1 = [S4+0000]
	ErrorToCallFunction(0x04001ACC);

_04001AD0:	// 4001ad0: <4a684210>	VADD      vec08 = vec08 + vec08[1q]
	ErrorToCallFunction(0x04001AD0);

_04001AD4:	// 4001ad4: <86ad0008>	LH        T5 = [S5+0008]
	ErrorToCallFunction(0x04001AD4);

_04001AD8:	// 4001ad8: <4a6739d0>	VADD      vec07 = vec07 + vec07[1q]
	ErrorToCallFunction(0x04001AD8);

_04001ADC:	// 4001adc: <86850008>	LH        A1 = [S4+0008]
	ErrorToCallFunction(0x04001ADC);

_04001AE0:	// 4001ae0: <4a663190>	VADD      vec06 = vec06 + vec06[1q]
	ErrorToCallFunction(0x04001AE0);

_04001AE4:	// 4001ae4: <86b00002>	LH        S0 = [S5+0002]
	ErrorToCallFunction(0x04001AE4);

_04001AE8:	// 4001ae8: <4a652950>	VADD      vec05 = vec05 + vec05[1q]
	ErrorToCallFunction(0x04001AE8);

_04001AEC:	// 4001aec: <86880002>	LH        T0 = [S4+0002]
	ErrorToCallFunction(0x04001AEC);

_04001AF0:	// 4001af0: <4ac84210>	VADD      vec08 = vec08 + vec08[2h]
	ErrorToCallFunction(0x04001AF0);

_04001AF4:	// 4001af4: <86ac000a>	LH        T4 = [S5+000a]
	ErrorToCallFunction(0x04001AF4);

_04001AF8:	// 4001af8: <4ac739d0>	VADD      vec07 = vec07 + vec07[2h]
	ErrorToCallFunction(0x04001AF8);

_04001AFC:	// 4001afc: <8684000a>	LH        A0 = [S4+000a]
	ErrorToCallFunction(0x04001AFC);

_04001B00:	// 4001b00: <4ac63190>	VADD      vec06 = vec06 + vec06[2h]
	ErrorToCallFunction(0x04001B00);

_04001B04:	// 4001b04: <86af0004>	LH        T7 = [S5+0004]
	ErrorToCallFunction(0x04001B04);

_04001B08:	// 4001b08: <4ac52950>	VADD      vec05 = vec05 + vec05[2h]
	ErrorToCallFunction(0x04001B08);

_04001B0C:	// 4001b0c: <86870004>	LH        A3 = [S4+0004]
	ErrorToCallFunction(0x04001B0C);

_04001B10:	// 4001b10: <4a88e906>	VMUDN     vec04 = ( acc = vec29 * vec08[0h]      ) >> 16
	ErrorToCallFunction(0x04001B10);

_04001B14:	// 4001b14: <86ab000c>	LH        T3 = [S5+000c]
	ErrorToCallFunction(0x04001B14);

_04001B18:	// 4001b18: <4a87e10e>	VMADN     vec04 = ( acc+= vec28 * vec07[0h] )
	ErrorToCallFunction(0x04001B18);

_04001B1C:	// 4001b1c: <8683000c>	LH        V1 = [S4+000c]
	ErrorToCallFunction(0x04001B1C);

_04001B20:	// 4001b20: <4a86d90e>	VMADN     vec04 = ( acc+= vec27 * vec06[0h] )
	ErrorToCallFunction(0x04001B20);

_04001B24:	// 4001b24: <86ae0006>	LH        T6 = [S5+0006]
	ErrorToCallFunction(0x04001B24);

_04001B28:	// 4001b28: <4a85d10e>	VMADN     vec04 = ( acc+= vec26 * vec05[0h] )
	ErrorToCallFunction(0x04001B28);

_04001B2C:	// 4001b2c: <86860006>	LH        A2 = [S4+0006]
	ErrorToCallFunction(0x04001B2C);

_04001B30:	// 4001b30: <86aa000e>	LH        T2 = [S5+000e]
	ErrorToCallFunction(0x04001B30);

_04001B34:	// 4001b34: <2252fff0>	ADDI      S2 = S2 + fff0
	ErrorToCallFunction(0x04001B34);

_04001B38:	// 4001b38: <ea642000>	SQV       [S3 + 0x00] = vec04 <00>
	ErrorToCallFunction(0x04001B38);

_04001B3C:	// 4001b3c: <1a400003>	BLEZ      (R0<=0) --> 1b4c
	sp_reg_pc = 0x04001B3C;
	if ((_s32)state.r[S2] <= 0)
	{
		state.r[V0] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x0000000E) & 0xfff);
		goto _04001B4C;
	}


_04001B40:	// 4001b40: <8682000e>	LH        V0 = [S4+000e]
	state.r[V0] = (_s32)(_s16)Load16_DMEM((state.r[S4] + 0x0000000E) & 0xfff);


_04001B44:	// 4001b44: <09000693>	J         04001a4c
	state.r[S3] = state.r[S3] + 0x0010;
	goto _04001A4C;


_04001B48:	// 4001b48: <22730010>	ADDI      S3 = S3 + 0010
	state.r[S3] = state.r[S3] + 0x0010;


_04001B4C:	// 4001b4c: <eaf70804>	SSV       [S7 + 0x08] = vec23 <00>
	Save16_DMEM(state.v[23].U16[7], (0x00000008 + state.r[S7]) & 0xfff);


_04001B50:	// 4001b50: <ca301800>	LDV       vec16 <00> = [S1 + 0x00]
	rsp_ldv_compiler((state.r[S1] & 0xFFF), 16, 8);


_04001B54:	// 4001b54: <eaf01800>	SDV       [S7 + 0x00] = vec16 <00>
	{
		_u32	addr = (0x00000000 + state.r[S7]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[16].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[16].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[16].U32[0x00000003];
		}
	}


_04001B58:	// 4001b58: <87060000>	LH        A2 = [T8+0000]
	state.r[A2] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000000) & 0xfff);


_04001B5C:	// 4001b5c: <22310008>	ADDI      S1 = S1 + 0008
	state.r[S1] = state.r[S1] + 0x0008;


_04001B60:	// 4001b60: <02262822>	SUB       A1 = S1-A2
	state.r[A1] = (state.r[S1] - state.r[A2]);


_04001B64:	// 4001b64: <30a4000f>	ANDI      A0 = A1 & 000f
	state.r[A0] = (state.r[A1] & 0x0000000F);


_04001B68:	// 4001b68: <02248822>	SUB       S1 = S1-A0
	state.r[S1] = (state.r[S1] - state.r[A0]);


_04001B6C:	// 4001b6c: <10800002>	BEQ       (R0==A0) --> 1b78
	sp_reg_pc = 0x04001B6C;
	if (state.r[A0] == 0)
	{
		state.r[A3] = 0 + 0x0010;
		goto _04001B78;
	}


_04001B70:	// 4001b70: <20070010>	ADDI      A3 = R0 + 0010
	state.r[A3] = 0 + 0x0010;


_04001B74:	// 4001b74: <00e42022>	SUB       A0 = A3-A0
	state.r[A0] = (state.r[A3] - state.r[A0]);


_04001B78:	// 4001b78: <a6e4000a>	SH        [S7+000a] = A0
	Save16_DMEM((_u16)state.r[A0], (state.r[S7] + 0x0000000A) & 0xfff);


_04001B7C:	// 4001b7c: <ca231800>	LDV       vec03 <00> = [S1 + 0x00]
	rsp_ldv_compiler((state.r[S1] & 0xFFF), 3, 8);


_04001B80:	// 4001b80: <ca231c01>	LDV       vec03 <08> = [S1 + 0x08]
	rsp_ldv_compiler((state.r[S1] + 0x00000008) & 0xFFF, 3, 0);


_04001B84:	// 4001b84: <eae32001>	SQV       [S7 + 0x10] = vec03 <00>
	{
		_u32    addr = (0x00000010 + state.r[S7]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[3].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[3].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[3].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[3].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[3].U64[0] & temp1);
			value2 |= (state.v[3].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001B88:	// 4001b88: <8ee20040>	LW        V0 = [S7+0040]
	state.r[V0] = (_s32)Load32_DMEM((state.r[S7] + 0x00000040) & 0xfff);


_04001B8C:	// 4001b8c: <22e10000>	ADDI      AT = S7 + 0000
	state.r[AT] = state.r[S7] + 0x0000;


_04001B90:	// 4001b90: <0d000470>	JAL	    040011c0
	state.r[V1] = 0 + 0x001F;
	sp_reg_pc = 0x04001B90;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _040011C0;


_04001B94:	// 4001b94: <2003001f>	ADDI      V1 = R0 + 001f
	state.r[V1] = 0 + 0x001F;


_04001B98:	// 4001b98: <09000446>	J         04001118
	goto _04001118;


_04001B9C:	// 4001b9c: <00000000>	NOP       


_04001BA0:	// 4001ba0: <3c0400ff>	LUI       A0 = 0x00ff0000
	state.r[A0] = 0x00FF0000;


_04001BA4:	// 4001ba4: <3484ffff>	ORI       A0 = A0 | 0xffff
	state.r[A0] = (state.r[A0] | 0x0000FFFF);


_04001BA8:	// 4001ba8: <03241024>	AND       V0 = T9 & A0
	state.r[V0] = (state.r[T9] & state.r[A0]);


_04001BAC:	// 4001bac: <00192e02>	SRL       A1 = T9 >> 24
	state.r[A1] = ((_u32)state.r[T9] >> 24);


_04001BB0:	// 4001bb0: <00052880>	SLL       A1 = A1 << 2
	state.r[A1] = ((_u32)state.r[A1] << 2);


_04001BB4:	// 4001bb4: <8ca60320>	LW        A2 = [A1+0320]
	state.r[A2] = (_s32)Load32_DMEM((state.r[A1] + 0x00000320) & 0xfff);


_04001BB8:	// 4001bb8: <00461020>	ADD       V0 = V0+A2
	state.r[V0] = (state.r[V0] + state.r[A2]);


_04001BBC:	// 4001bbc: <22e10000>	ADDI      AT = S7 + 0000
	state.r[AT] = state.r[S7] + 0x0000;


_04001BC0:	// 4001bc0: <2003004f>	ADDI      V1 = R0 + 004f
	state.r[V1] = 0 + 0x004F;


_04001BC4:	// 4001bc4: <4a00002c>	VXOR      vec00 = vec00 xor vec00[<none>]
	rsp_cop2_vxor(&state.v[0], &state.v[0], &state.v[0]);


_04001BC8:	// 4001bc8: <200b0050>	ADDI      T3 = R0 + 0050
	state.r[T3] = 0 + 0x0050;


_04001BCC:	// 4001bcc: <c97f2001>	LQV       vec31 <00> = [T3 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[T3]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[31].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[31].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[31].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[31].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[31].U64[0] = state.v[31].U64[0] & ~temp1;
			state.v[31].U64[1] = state.v[31].U64[1] & ~temp2;
			state.v[31].U64[0] = state.v[31].U64[0] | value1;
			state.v[31].U64[1] = state.v[31].U64[1] | value2;
		}
	}


_04001BD0:	// 4001bd0: <c80a2000>	LQV       vec10 <00> = [R0 + 0x00]
	{
		_u32 addr = (0x00000000 + 0);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[10].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[10].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[10].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[10].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[10].U64[0] = state.v[10].U64[0] & ~temp1;
			state.v[10].U64[1] = state.v[10].U64[1] & ~temp2;
			state.v[10].U64[0] = state.v[10].U64[0] | value1;
			state.v[10].U64[1] = state.v[10].U64[1] | value2;
		}
	}


_04001BD4:	// 4001bd4: <001a6402>	SRL       T4 = K0 >> 16
	state.r[T4] = ((_u32)state.r[K0] >> 16);


_04001BD8:	// 4001bd8: <318a0001>	ANDI      T2 = T4 & 0001
	state.r[T2] = (state.r[T4] & 0x00000001);


_04001BDC:	// 4001bdc: <11400003>	BEQ       (R0==T2) --> 1bec
	sp_reg_pc = 0x04001BDC;
	if (state.r[T2] == 0)
	{
		{
			_u32 addr = (0x00000010 + state.r[T8]);
			int shifter = ((addr & 0xf) << 3);

			if (shifter == 0 && (addr&3) == 0 )
			{
				addr &= 0xfff;
				state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
				state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
				state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
				state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
			}
			else
			{
				_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
				_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
				_u64		value1 = Load64_DMEM(addr+8);
				_u64		value2 = Load64_DMEM(addr);
				if (shifter > 0x40)
				{
					temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
					temp1 = 0;
				} else {
					temp1 = ((temp1 >> shifter) << shifter);
				}
				value1 = value1 & temp1;
				value2 = value2 & temp2;

				state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
				state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
				state.v[24].U64[0] = state.v[24].U64[0] | value1;
				state.v[24].U64[1] = state.v[24].U64[1] | value2;
			}
		}
		goto _04001BEC;
	}


_04001BE0:	// 4001be0: <cb182001>	LQV       vec24 <00> = [T8 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[T8]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
			state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
			state.v[24].U64[0] = state.v[24].U64[0] | value1;
			state.v[24].U64[1] = state.v[24].U64[1] | value2;
		}
	}


_04001BE4:	// 4001be4: <09000706>	J         04001c18
	goto _04001C18;


_04001BE8:	// 4001be8: <00000000>	NOP       


_04001BEC:	// 4001bec: <0d000465>	JAL	    04001194
	sp_reg_pc = 0x04001BEC;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001194;


_04001BF0:	// 4001bf0: <00000000>	NOP       


_04001BF4:	// 4001bf4: <40053000>	MFC0      A2 = SP DMA full
	state.r[A1] = 0;


_04001BF8:	// 4001bf8: <14a0fffe>	BNE       (R0!=A1) --> 1bf4
	sp_reg_pc = 0x04001BF8;
	if (state.r[A1] != 0)
	{
		goto _04001BF4;
	}


_04001BFC:	// 4001bfc: <00000000>	NOP       


_04001C00:	// 4001c00: <0000b020>	ADD       S6 = R0+R0
	state.r[S6] = (0 + 0);


_04001C04:	// 4001c04: <caf42000>	LQV       vec20 <00> = [S7 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S7]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[20].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[20].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[20].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[20].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[20].U64[0] = state.v[20].U64[0] & ~temp1;
			state.v[20].U64[1] = state.v[20].U64[1] & ~temp2;
			state.v[20].U64[0] = state.v[20].U64[0] | value1;
			state.v[20].U64[1] = state.v[20].U64[1] | value2;
		}
	}


_04001C08:	// 4001c08: <caf52001>	LQV       vec21 <00> = [S7 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[S7]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[21].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[21].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[21].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[21].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[21].U64[0] = state.v[21].U64[0] & ~temp1;
			state.v[21].U64[1] = state.v[21].U64[1] & ~temp2;
			state.v[21].U64[0] = state.v[21].U64[0] | value1;
			state.v[21].U64[1] = state.v[21].U64[1] | value2;
		}
	}


_04001C0C:	// 4001c0c: <caf22002>	LQV       vec18 <00> = [S7 + 0x20]
	{
		_u32 addr = (0x00000020 + state.r[S7]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[18].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[18].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[18].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[18].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[18].U64[0] = state.v[18].U64[0] & ~temp1;
			state.v[18].U64[1] = state.v[18].U64[1] & ~temp2;
			state.v[18].U64[0] = state.v[18].U64[0] | value1;
			state.v[18].U64[1] = state.v[18].U64[1] | value2;
		}
	}


_04001C10:	// 4001c10: <caf32003>	LQV       vec19 <00> = [S7 + 0x30]
	{
		_u32 addr = (0x00000030 + state.r[S7]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[19].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[19].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[19].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[19].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[19].U64[0] = state.v[19].U64[0] & ~temp1;
			state.v[19].U64[1] = state.v[19].U64[1] & ~temp2;
			state.v[19].U64[0] = state.v[19].U64[0] | value1;
			state.v[19].U64[1] = state.v[19].U64[1] | value2;
		}
	}


_04001C14:	// 4001c14: <caf82004>	LQV       vec24 <00> = [S7 + 0x40]
	{
		_u32 addr = (0x00000040 + state.r[S7]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
			state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
			state.v[24].U64[0] = state.v[24].U64[0] | value1;
			state.v[24].U64[1] = state.v[24].U64[1] | value2;
		}
	}


_04001C18:	// 4001c18: <14000005>	BNE       (R0!=R0) --> 1c30
	sp_reg_pc = 0x04001C18;
	if (0 != 0)
	{
		goto _04001C30;
	}


_04001C1C:	// 4001c1c: <00000000>	NOP       


_04001C20:	// 4001c20: <40093000>	MFC0      A2 = DP CMD DMA end
	state.r[T1] = 0;


_04001C24:	// 4001c24: <1520fffe>	BNE       (R0!=T1) --> 1c20
	sp_reg_pc = 0x04001C24;
	if (state.r[T1] != 0)
	{
		goto _04001C20;
	}


_04001C28:	// 4001c28: <00000000>	NOP       


_04001C2C:	// 4001c2c: <0000b024>	AND       S6 = R0 & R0
	state.r[S6] = (0 & 0);


_04001C30:	// 4001c30: <870d0000>	LH        T5 = [T8+0000]
	state.r[T5] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000000) & 0xfff);


_04001C34:	// 4001c34: <87130002>	LH        S3 = [T8+0002]
	state.r[S3] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000002) & 0xfff);


_04001C38:	// 4001c38: <8712000a>	LH        S2 = [T8+000a]
	state.r[S2] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x0000000A) & 0xfff);


_04001C3C:	// 4001c3c: <8711000c>	LH        S1 = [T8+000c]
	state.r[S1] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x0000000C) & 0xfff);


_04001C40:	// 4001c40: <8710000e>	LH        S0 = [T8+000e]
	state.r[S0] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x0000000E) & 0xfff);


_04001C44:	// 4001c44: <870e0004>	LH        T6 = [T8+0004]
	state.r[T6] = (_s32)(_s16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_04001C48:	// 4001c48: <200f0010>	ADDI      T7 = R0 + 0010
	state.r[T7] = 0 + 0x0010;


_04001C4C:	// 4001c4c: <4815c100>	MFC2      S5 = vec24 <02>
	state.r[S5] = (_s32)state.v[24].S16[6];


_04001C50:	// 4001c50: <4814c400>	MFC2      S4 = vec24 <08>
	state.r[S4] = (_s32)state.v[24].S16[3];


_04001C54:	// 4001c54: <31890008>	ANDI      T1 = T4 & 0008
	state.r[T1] = (state.r[T4] & 0x00000008);


_04001C58:	// 4001c58: <1d200004>	BGTZ      (R0>0) --> 1c6c
	sp_reg_pc = 0x04001C58;
	if((_s32)state.r[T1] > 0)
	{
		goto _04001C6C;
	}


_04001C5C:	// 4001c5c: <00000000>	NOP       


_04001C60:	// 4001c60: <22f10050>	ADDI      S1 = S7 + 0050
	state.r[S1] = state.r[S7] + 0x0050;


_04001C64:	// 4001c64: <00118020>	ADD       S0 = R0+S1
	state.r[S0] = (0 + state.r[S1]);


_04001C68:	// 4001c68: <200f0000>	ADDI      T7 = R0 + 0000
	state.r[T7] = 0 + 0x0000;


_04001C6C:	// 4001c6c: <11400036>	BEQ       (R0==T2) --> 1d48
	sp_reg_pc = 0x04001C6C;
	if (state.r[T2] == 0)
	{
		{
			_u32 addr = (0x00000070 + state.r[T3]);
			int shifter = ((addr & 0xf) << 3);

			if (shifter == 0 && (addr&3) == 0 )
			{
				addr &= 0xfff;
				state.v[30].U32[0] = *(_u32 *)&pDMEM[addr+12];
				state.v[30].U32[1] = *(_u32 *)&pDMEM[addr+8];
				state.v[30].U32[2] = *(_u32 *)&pDMEM[addr+4];
				state.v[30].U32[3] = *(_u32 *)&pDMEM[addr];
			}
			else
			{
				_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
				_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
				_u64		value1 = Load64_DMEM(addr+8);
				_u64		value2 = Load64_DMEM(addr);
				if (shifter > 0x40)
				{
					temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
					temp1 = 0;
				} else {
					temp1 = ((temp1 >> shifter) << shifter);
				}
				value1 = value1 & temp1;
				value2 = value2 & temp2;

				state.v[30].U64[0] = state.v[30].U64[0] & ~temp1;
				state.v[30].U64[1] = state.v[30].U64[1] & ~temp2;
				state.v[30].U64[0] = state.v[30].U64[0] | value1;
				state.v[30].U64[1] = state.v[30].U64[1] | value2;
			}
		}
		goto _04001D48;
	}


_04001C70:	// 4001c70: <c97e2007>	LQV       vec30 <00> = [T3 + 0x70]
	{
		_u32 addr = (0x00000070 + state.r[T3]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[30].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[30].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[30].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[30].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[30].U64[0] = state.v[30].U64[0] & ~temp1;
			state.v[30].U64[1] = state.v[30].U64[1] & ~temp2;
			state.v[30].U64[0] = state.v[30].U64[0] | value1;
			state.v[30].U64[1] = state.v[30].U64[1] | value2;
		}
	}


_04001C74:	// 4001c74: <c9b12000>	LQV       vec17 <00> = [T5 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[T5]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[17].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[17].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[17].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[17].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[17].U64[0] = state.v[17].U64[0] & ~temp1;
			state.v[17].U64[1] = state.v[17].U64[1] & ~temp2;
			state.v[17].U64[0] = state.v[17].U64[0] | value1;
			state.v[17].U64[1] = state.v[17].U64[1] | value2;
		}
	}


_04001C78:	// 4001c78: <ca7d2000>	LQV       vec29 <00> = [S3 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S3]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[29].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[29].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[29].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[29].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[29].U64[0] = state.v[29].U64[0] & ~temp1;
			state.v[29].U64[1] = state.v[29].U64[1] & ~temp2;
			state.v[29].U64[0] = state.v[29].U64[0] | value1;
			state.v[29].U64[1] = state.v[29].U64[1] | value2;
		}
	}


_04001C7C:	// 4001c7c: <ca3b2000>	LQV       vec27 <00> = [S1 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}


_04001C80:	// 4001c80: <4a15ad6c>	VXOR      vec21 = vec21 xor vec21[<none>]
	rsp_cop2_vxor(&state.v[21], &state.v[21], &state.v[21]);


_04001C84:	// 4001c84: <cb140f03>	LSV       vec20 <14> = [T8 + 0x06]
	state.v[20].U16[0] = Load16_DMEM(0x00000006 + state.r[T8]);


_04001C88:	// 4001c88: <4b58f5c4>	VMUDL     vec23 = ( acc = (vec30 * vec24[2] >> 16)      )
	{
		_u16		s2value = state.v[24].U16[5];
		VMUDL_operation(0, state.v[23].U16[0], state.v[30].U16[0], s2value, 0, 1, 1, 1)
		VMUDL_operation(1, state.v[23].U16[1], state.v[30].U16[1], s2value, 0, 1, 1, 1)
		VMUDL_operation(2, state.v[23].U16[2], state.v[30].U16[2], s2value, 0, 1, 1, 1)
		VMUDL_operation(3, state.v[23].U16[3], state.v[30].U16[3], s2value, 0, 1, 1, 1)
		VMUDL_operation(4, state.v[23].U16[4], state.v[30].U16[4], s2value, 0, 1, 1, 1)
		VMUDL_operation(5, state.v[23].U16[5], state.v[30].U16[5], s2value, 0, 1, 1, 1)
		VMUDL_operation(6, state.v[23].U16[6], state.v[30].U16[6], s2value, 0, 1, 1, 1)
		VMUDL_operation(7, state.v[23].U16[7], state.v[30].U16[7], s2value, 0, 1, 1, 1)
	}


_04001C8C:	// 4001c8c: <4b38f5ce>	VMADN     vec23 = ( acc+= vec30 * vec24[1] )
	{
		_u16		s2value = state.v[24].U16[6];
		VMADN_operation(0, state.v[23].U16[0], state.v[30].U16[0], s2value, 1, 1, 1, 1)
		VMADN_operation(1, state.v[23].U16[1], state.v[30].U16[1], s2value, 1, 1, 1, 1)
		VMADN_operation(2, state.v[23].U16[2], state.v[30].U16[2], s2value, 1, 1, 1, 1)
		VMADN_operation(3, state.v[23].U16[3], state.v[30].U16[3], s2value, 1, 1, 1, 1)
		VMADN_operation(4, state.v[23].U16[4], state.v[30].U16[4], s2value, 1, 1, 1, 1)
		VMADN_operation(5, state.v[23].U16[5], state.v[30].U16[5], s2value, 1, 1, 1, 1)
		VMADN_operation(6, state.v[23].U16[6], state.v[30].U16[6], s2value, 1, 1, 1, 1)
		VMADN_operation(7, state.v[23].U16[7], state.v[30].U16[7], s2value, 1, 1, 1, 1)
	}


_04001C90:	// 4001c90: <4b00fd8d>	VMADM     vec22 = ( acc+= vec31 * vec00[0] ) >> 16
	{
		_u16		s2value = state.v[0].U16[7];
		VMADM_operation(0, state.v[22].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
		VMADM_operation(1, state.v[22].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
		VMADM_operation(2, state.v[22].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
		VMADM_operation(3, state.v[22].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
		VMADM_operation(4, state.v[22].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
		VMADM_operation(5, state.v[22].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
		VMADM_operation(6, state.v[22].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
		VMADM_operation(7, state.v[22].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
	}


_04001C94:	// 4001c94: <4bf5fd4d>	VMADM     vec21 = ( acc+= vec31 * vec21[7] ) >> 16
	{
		_u16		s2value = state.v[21].U16[0];
		VMADM_operation(0, state.v[21].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
		VMADM_operation(1, state.v[21].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
		VMADM_operation(2, state.v[21].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
		VMADM_operation(3, state.v[21].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
		VMADM_operation(4, state.v[21].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
		VMADM_operation(5, state.v[21].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
		VMADM_operation(6, state.v[21].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
		VMADM_operation(7, state.v[21].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
	}


_04001C98:	// 4001c98: <4bf4fd0f>	VMADH     vec20 = ( acc+= (vec31 * vec20[7]) << 16) >> 16
	{
		_u16		s2value = state.v[20].U16[0];
		VMADH_operation(0, state.v[20].U16[0], state.v[31].U16[0], s2value, 1, 1, 0, 1)
		VMADH_operation(1, state.v[20].U16[1], state.v[31].U16[1], s2value, 1, 1, 0, 1)
		VMADH_operation(2, state.v[20].U16[2], state.v[31].U16[2], s2value, 1, 1, 0, 1)
		VMADH_operation(3, state.v[20].U16[3], state.v[31].U16[3], s2value, 1, 1, 0, 1)
		VMADH_operation(4, state.v[20].U16[4], state.v[31].U16[4], s2value, 1, 1, 0, 1)
		VMADH_operation(5, state.v[20].U16[5], state.v[31].U16[5], s2value, 1, 1, 0, 1)
		VMADH_operation(6, state.v[20].U16[6], state.v[31].U16[6], s2value, 1, 1, 0, 1)
		VMADH_operation(7, state.v[20].U16[7], state.v[31].U16[7], s2value, 1, 1, 0, 1)
	}


_04001C9C:	// 4001c9c: <1ea00004>	BGTZ      (R0>0) --> 1cb0
	sp_reg_pc = 0x04001C9C;
	if((_s32)state.r[S5] > 0)
	{
		{
			_u16		s2value = state.v[0].U16[7];
			VMADN_operation(0, state.v[21].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
			VMADN_operation(1, state.v[21].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
			VMADN_operation(2, state.v[21].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
			VMADN_operation(3, state.v[21].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
			VMADN_operation(4, state.v[21].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
			VMADN_operation(5, state.v[21].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
			VMADN_operation(6, state.v[21].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
			VMADN_operation(7, state.v[21].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
		}
		goto _04001CB0;
	}


_04001CA0:	// 4001ca0: <4b00fd4e>	VMADN     vec21 = ( acc+= vec31 * vec00[0] )
	{
		_u16		s2value = state.v[0].U16[7];
		VMADN_operation(0, state.v[21].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
		VMADN_operation(1, state.v[21].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
		VMADN_operation(2, state.v[21].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
		VMADN_operation(3, state.v[21].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
		VMADN_operation(4, state.v[21].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
		VMADN_operation(5, state.v[21].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
		VMADN_operation(6, state.v[21].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
		VMADN_operation(7, state.v[21].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
	}


_04001CA4:	// 4001ca4: <4b18a523>	VGE       vec20 = (vec20 >= vec24[0])
	rsp_cop2_vge_element(&state.v[20], &state.v[20], &state.v[24].U16[7]);


_04001CA8:	// 4001ca8: <0900072d>	J         04001cb4
	goto _04001CB4;


_04001CAC:	// 4001cac: <00000000>	NOP       


_04001CB0:	// 4001cb0: <4b18a524>	VCL ?-?
	rsp_cop2_vcl_element(&state.v[20], &state.v[20], &state.v[24].U16[7]);


_04001CB4:	// 4001cb4: <4bd8a400>	VMULF     vec16 = ( acc = (vec20 * vec24[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[1];
		VMULF_operation(0, state.v[16].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[16].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[16].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[16].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[16].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[16].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[16].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[16].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
	}


_04001CB8:	// 4001cb8: <4bf8a3c0>	VMULF     vec15 = ( acc = (vec20 * vec24[7]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[0];
		VMULF_operation(0, state.v[15].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[15].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[15].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[15].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[15].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[15].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[15].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[15].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
	}


_04001CBC:	// 4001cbc: <4bcaef40>	VMULF     vec29 = ( acc = (vec29 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[29].U16[0], state.v[29].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[29].U16[1], state.v[29].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[29].U16[2], state.v[29].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[29].U16[3], state.v[29].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[29].U16[4], state.v[29].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[29].U16[5], state.v[29].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[29].U16[6], state.v[29].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[29].U16[7], state.v[29].U16[7], s2value, 0, 1, 1, 1)
	}


_04001CC0:	// 4001cc0: <4a108f48>	VMACF     vec29 = ( acc += (vec17 * vec16[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[29].U16[0], state.v[17].U16[0], state.v[16].U16[0], 1, 0, 0, 1)
		VMACF_operation(1, state.v[29].U16[1], state.v[17].U16[1], state.v[16].U16[1], 1, 0, 0, 1)
		VMACF_operation(2, state.v[29].U16[2], state.v[17].U16[2], state.v[16].U16[2], 1, 0, 0, 1)
		VMACF_operation(3, state.v[29].U16[3], state.v[17].U16[3], state.v[16].U16[3], 1, 0, 0, 1)
		VMACF_operation(4, state.v[29].U16[4], state.v[17].U16[4], state.v[16].U16[4], 1, 0, 0, 1)
		VMACF_operation(5, state.v[29].U16[5], state.v[17].U16[5], state.v[16].U16[5], 1, 0, 0, 1)
		VMACF_operation(6, state.v[29].U16[6], state.v[17].U16[6], state.v[16].U16[6], 1, 0, 0, 1)
		VMACF_operation(7, state.v[29].U16[7], state.v[17].U16[7], state.v[16].U16[7], 1, 0, 0, 1)
	}


_04001CC4:	// 4001cc4: <4bcadec0>	VMULF     vec27 = ( acc = (vec27 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[27].U16[0], state.v[27].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[27].U16[1], state.v[27].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[27].U16[2], state.v[27].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[27].U16[3], state.v[27].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[27].U16[4], state.v[27].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[27].U16[5], state.v[27].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[27].U16[6], state.v[27].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[27].U16[7], state.v[27].U16[7], s2value, 0, 1, 1, 1)
	}


_04001CC8:	// 4001cc8: <4a0f8ec8>	VMACF     vec27 = ( acc += (vec17 * vec15[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[27].U16[0], state.v[17].U16[0], state.v[15].U16[0], 1, 0, 0, 1)
		VMACF_operation(1, state.v[27].U16[1], state.v[17].U16[1], state.v[15].U16[1], 1, 0, 0, 1)
		VMACF_operation(2, state.v[27].U16[2], state.v[17].U16[2], state.v[15].U16[2], 1, 0, 0, 1)
		VMACF_operation(3, state.v[27].U16[3], state.v[17].U16[3], state.v[15].U16[3], 1, 0, 0, 1)
		VMACF_operation(4, state.v[27].U16[4], state.v[17].U16[4], state.v[15].U16[4], 1, 0, 0, 1)
		VMACF_operation(5, state.v[27].U16[5], state.v[17].U16[5], state.v[15].U16[5], 1, 0, 0, 1)
		VMACF_operation(6, state.v[27].U16[6], state.v[17].U16[6], state.v[15].U16[6], 1, 0, 0, 1)
		VMACF_operation(7, state.v[27].U16[7], state.v[17].U16[7], state.v[15].U16[7], 1, 0, 0, 1)
	}


_04001CCC:	// 4001ccc: <ea7d2000>	SQV       [S3 + 0x00] = vec29 <00>
	{
		_u32    addr = (0x00000000 + state.r[S3]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[29].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[29].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[29].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[29].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[29].U64[0] & temp1);
			value2 |= (state.v[29].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001CD0:	// 4001cd0: <ea3b2000>	SQV       [S1 + 0x00] = vec27 <00>
	{
		_u32    addr = (0x00000000 + state.r[S1]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[27].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[27].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[27].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[27].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[27].U64[0] & temp1);
			value2 |= (state.v[27].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001CD4:	// 4001cd4: <ca5c2000>	LQV       vec28 <00> = [S2 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S2]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[28].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[28].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[28].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[28].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[28].U64[0] = state.v[28].U64[0] & ~temp1;
			state.v[28].U64[1] = state.v[28].U64[1] & ~temp2;
			state.v[28].U64[0] = state.v[28].U64[0] | value1;
			state.v[28].U64[1] = state.v[28].U64[1] | value2;
		}
	}


_04001CD8:	// 4001cd8: <ca1a2000>	LQV       vec26 <00> = [S0 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[26].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[26].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[26].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[26].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[26].U64[0] = state.v[26].U64[0] & ~temp1;
			state.v[26].U64[1] = state.v[26].U64[1] & ~temp2;
			state.v[26].U64[0] = state.v[26].U64[0] | value1;
			state.v[26].U64[1] = state.v[26].U64[1] | value2;
		}
	}


_04001CDC:	// 4001cdc: <4a139cec>	VXOR      vec19 = vec19 xor vec19[<none>]
	rsp_cop2_vxor(&state.v[19], &state.v[19], &state.v[19]);


_04001CE0:	// 4001ce0: <cb120f04>	LSV       vec18 <14> = [T8 + 0x08]
	state.v[18].U16[0] = Load16_DMEM(0x00000008 + state.r[T8]);


_04001CE4:	// 4001ce4: <4bb8f5c4>	VMUDL     vec23 = ( acc = (vec30 * vec24[5] >> 16)      )
	{
		_u16		s2value = state.v[24].U16[2];
		VMUDL_operation(0, state.v[23].U16[0], state.v[30].U16[0], s2value, 0, 1, 1, 1)
		VMUDL_operation(1, state.v[23].U16[1], state.v[30].U16[1], s2value, 0, 1, 1, 1)
		VMUDL_operation(2, state.v[23].U16[2], state.v[30].U16[2], s2value, 0, 1, 1, 1)
		VMUDL_operation(3, state.v[23].U16[3], state.v[30].U16[3], s2value, 0, 1, 1, 1)
		VMUDL_operation(4, state.v[23].U16[4], state.v[30].U16[4], s2value, 0, 1, 1, 1)
		VMUDL_operation(5, state.v[23].U16[5], state.v[30].U16[5], s2value, 0, 1, 1, 1)
		VMUDL_operation(6, state.v[23].U16[6], state.v[30].U16[6], s2value, 0, 1, 1, 1)
		VMUDL_operation(7, state.v[23].U16[7], state.v[30].U16[7], s2value, 0, 1, 1, 1)
	}


_04001CE8:	// 4001ce8: <4b98f5ce>	VMADN     vec23 = ( acc+= vec30 * vec24[4] )
	{
		_u16		s2value = state.v[24].U16[3];
		VMADN_operation(0, state.v[23].U16[0], state.v[30].U16[0], s2value, 1, 1, 1, 1)
		VMADN_operation(1, state.v[23].U16[1], state.v[30].U16[1], s2value, 1, 1, 1, 1)
		VMADN_operation(2, state.v[23].U16[2], state.v[30].U16[2], s2value, 1, 1, 1, 1)
		VMADN_operation(3, state.v[23].U16[3], state.v[30].U16[3], s2value, 1, 1, 1, 1)
		VMADN_operation(4, state.v[23].U16[4], state.v[30].U16[4], s2value, 1, 1, 1, 1)
		VMADN_operation(5, state.v[23].U16[5], state.v[30].U16[5], s2value, 1, 1, 1, 1)
		VMADN_operation(6, state.v[23].U16[6], state.v[30].U16[6], s2value, 1, 1, 1, 1)
		VMADN_operation(7, state.v[23].U16[7], state.v[30].U16[7], s2value, 1, 1, 1, 1)
	}


_04001CEC:	// 4001cec: <4b00fd8d>	VMADM     vec22 = ( acc+= vec31 * vec00[0] ) >> 16
	{
		_u16		s2value = state.v[0].U16[7];
		VMADM_operation(0, state.v[22].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
		VMADM_operation(1, state.v[22].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
		VMADM_operation(2, state.v[22].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
		VMADM_operation(3, state.v[22].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
		VMADM_operation(4, state.v[22].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
		VMADM_operation(5, state.v[22].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
		VMADM_operation(6, state.v[22].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
		VMADM_operation(7, state.v[22].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
	}


_04001CF0:	// 4001cf0: <4bf3fccd>	VMADM     vec19 = ( acc+= vec31 * vec19[7] ) >> 16
	{
		_u16		s2value = state.v[19].U16[0];
		VMADM_operation(0, state.v[19].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
		VMADM_operation(1, state.v[19].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
		VMADM_operation(2, state.v[19].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
		VMADM_operation(3, state.v[19].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
		VMADM_operation(4, state.v[19].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
		VMADM_operation(5, state.v[19].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
		VMADM_operation(6, state.v[19].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
		VMADM_operation(7, state.v[19].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
	}


_04001CF4:	// 4001cf4: <4bf2fc8f>	VMADH     vec18 = ( acc+= (vec31 * vec18[7]) << 16) >> 16
	{
		_u16		s2value = state.v[18].U16[0];
		VMADH_operation(0, state.v[18].U16[0], state.v[31].U16[0], s2value, 1, 1, 0, 1)
		VMADH_operation(1, state.v[18].U16[1], state.v[31].U16[1], s2value, 1, 1, 0, 1)
		VMADH_operation(2, state.v[18].U16[2], state.v[31].U16[2], s2value, 1, 1, 0, 1)
		VMADH_operation(3, state.v[18].U16[3], state.v[31].U16[3], s2value, 1, 1, 0, 1)
		VMADH_operation(4, state.v[18].U16[4], state.v[31].U16[4], s2value, 1, 1, 0, 1)
		VMADH_operation(5, state.v[18].U16[5], state.v[31].U16[5], s2value, 1, 1, 0, 1)
		VMADH_operation(6, state.v[18].U16[6], state.v[31].U16[6], s2value, 1, 1, 0, 1)
		VMADH_operation(7, state.v[18].U16[7], state.v[31].U16[7], s2value, 1, 1, 0, 1)
	}


_04001CF8:	// 4001cf8: <1e800004>	BGTZ      (R0>0) --> 1d0c
	sp_reg_pc = 0x04001CF8;
	if((_s32)state.r[S4] > 0)
	{
		{
			_u16		s2value = state.v[0].U16[7];
			VMADN_operation(0, state.v[19].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
			VMADN_operation(1, state.v[19].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
			VMADN_operation(2, state.v[19].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
			VMADN_operation(3, state.v[19].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
			VMADN_operation(4, state.v[19].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
			VMADN_operation(5, state.v[19].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
			VMADN_operation(6, state.v[19].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
			VMADN_operation(7, state.v[19].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
		}
		goto _04001D0C;
	}


_04001CFC:	// 4001cfc: <4b00fcce>	VMADN     vec19 = ( acc+= vec31 * vec00[0] )
	{
		_u16		s2value = state.v[0].U16[7];
		VMADN_operation(0, state.v[19].U16[0], state.v[31].U16[0], s2value, 1, 1, 1, 1)
		VMADN_operation(1, state.v[19].U16[1], state.v[31].U16[1], s2value, 1, 1, 1, 1)
		VMADN_operation(2, state.v[19].U16[2], state.v[31].U16[2], s2value, 1, 1, 1, 1)
		VMADN_operation(3, state.v[19].U16[3], state.v[31].U16[3], s2value, 1, 1, 1, 1)
		VMADN_operation(4, state.v[19].U16[4], state.v[31].U16[4], s2value, 1, 1, 1, 1)
		VMADN_operation(5, state.v[19].U16[5], state.v[31].U16[5], s2value, 1, 1, 1, 1)
		VMADN_operation(6, state.v[19].U16[6], state.v[31].U16[6], s2value, 1, 1, 1, 1)
		VMADN_operation(7, state.v[19].U16[7], state.v[31].U16[7], s2value, 1, 1, 1, 1)
	}


_04001D00:	// 4001d00: <4b7894a3>	VGE       vec18 = (vec18 >= vec24[3])
	rsp_cop2_vge_element(&state.v[18], &state.v[18], &state.v[24].U16[4]);


_04001D04:	// 4001d04: <09000744>	J         04001d10
	goto _04001D10;


_04001D08:	// 4001d08: <00000000>	NOP       


_04001D0C:	// 4001d0c: <4b7894a4>	VCL ?-?
	rsp_cop2_vcl_element(&state.v[18], &state.v[18], &state.v[24].U16[4]);


_04001D10:	// 4001d10: <4bd89400>	VMULF     vec16 = ( acc = (vec18 * vec24[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[1];
		VMULF_operation(0, state.v[16].U16[0], state.v[18].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[16].U16[1], state.v[18].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[16].U16[2], state.v[18].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[16].U16[3], state.v[18].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[16].U16[4], state.v[18].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[16].U16[5], state.v[18].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[16].U16[6], state.v[18].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[16].U16[7], state.v[18].U16[7], s2value, 1, 0, 0, 1)
	}


_04001D14:	// 4001d14: <4bf893c0>	VMULF     vec15 = ( acc = (vec18 * vec24[7]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[0];
		VMULF_operation(0, state.v[15].U16[0], state.v[18].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[15].U16[1], state.v[18].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[15].U16[2], state.v[18].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[15].U16[3], state.v[18].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[15].U16[4], state.v[18].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[15].U16[5], state.v[18].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[15].U16[6], state.v[18].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[15].U16[7], state.v[18].U16[7], s2value, 1, 0, 0, 1)
	}


_04001D18:	// 4001d18: <4bcae700>	VMULF     vec28 = ( acc = (vec28 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[28].U16[0], state.v[28].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[28].U16[1], state.v[28].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[28].U16[2], state.v[28].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[28].U16[3], state.v[28].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[28].U16[4], state.v[28].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[28].U16[5], state.v[28].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[28].U16[6], state.v[28].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[28].U16[7], state.v[28].U16[7], s2value, 0, 1, 1, 1)
	}


_04001D1C:	// 4001d1c: <4a108f08>	VMACF     vec28 = ( acc += (vec17 * vec16[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[28].U16[0], state.v[17].U16[0], state.v[16].U16[0], 1, 0, 0, 1)
		VMACF_operation(1, state.v[28].U16[1], state.v[17].U16[1], state.v[16].U16[1], 1, 0, 0, 1)
		VMACF_operation(2, state.v[28].U16[2], state.v[17].U16[2], state.v[16].U16[2], 1, 0, 0, 1)
		VMACF_operation(3, state.v[28].U16[3], state.v[17].U16[3], state.v[16].U16[3], 1, 0, 0, 1)
		VMACF_operation(4, state.v[28].U16[4], state.v[17].U16[4], state.v[16].U16[4], 1, 0, 0, 1)
		VMACF_operation(5, state.v[28].U16[5], state.v[17].U16[5], state.v[16].U16[5], 1, 0, 0, 1)
		VMACF_operation(6, state.v[28].U16[6], state.v[17].U16[6], state.v[16].U16[6], 1, 0, 0, 1)
		VMACF_operation(7, state.v[28].U16[7], state.v[17].U16[7], state.v[16].U16[7], 1, 0, 0, 1)
	}


_04001D20:	// 4001d20: <4bcad680>	VMULF     vec26 = ( acc = (vec26 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[26].U16[0], state.v[26].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[26].U16[1], state.v[26].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[26].U16[2], state.v[26].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[26].U16[3], state.v[26].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[26].U16[4], state.v[26].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[26].U16[5], state.v[26].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[26].U16[6], state.v[26].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[26].U16[7], state.v[26].U16[7], s2value, 0, 1, 1, 1)
	}


_04001D24:	// 4001d24: <4a0f8e88>	VMACF     vec26 = ( acc += (vec17 * vec15[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[26].U16[0], state.v[17].U16[0], state.v[15].U16[0], 1, 1, 1, 1)
		VMACF_operation(1, state.v[26].U16[1], state.v[17].U16[1], state.v[15].U16[1], 1, 1, 1, 1)
		VMACF_operation(2, state.v[26].U16[2], state.v[17].U16[2], state.v[15].U16[2], 1, 1, 1, 1)
		VMACF_operation(3, state.v[26].U16[3], state.v[17].U16[3], state.v[15].U16[3], 1, 1, 1, 1)
		VMACF_operation(4, state.v[26].U16[4], state.v[17].U16[4], state.v[15].U16[4], 1, 1, 1, 1)
		VMACF_operation(5, state.v[26].U16[5], state.v[17].U16[5], state.v[15].U16[5], 1, 1, 1, 1)
		VMACF_operation(6, state.v[26].U16[6], state.v[17].U16[6], state.v[15].U16[6], 1, 1, 1, 1)
		VMACF_operation(7, state.v[26].U16[7], state.v[17].U16[7], state.v[15].U16[7], 1, 1, 1, 1)
	}


_04001D28:	// 4001d28: <ea5c2000>	SQV       [S2 + 0x00] = vec28 <00>
	{
		_u32    addr = (0x00000000 + state.r[S2]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[28].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[28].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[28].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[28].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[28].U64[0] & temp1);
			value2 |= (state.v[28].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001D2C:	// 4001d2c: <ea1a2000>	SQV       [S0 + 0x00] = vec26 <00>
	{
		_u32    addr = (0x00000000 + state.r[S0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[26].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[26].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[26].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[26].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[26].U64[0] & temp1);
			value2 |= (state.v[26].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001D30:	// 4001d30: <21cefff0>	ADDI      T6 = T6 + fff0
	state.r[T6] = state.r[T6] + 0xFFFFFFF0;


_04001D34:	// 4001d34: <21ad0010>	ADDI      T5 = T5 + 0010
	state.r[T5] = state.r[T5] + 0x0010;


_04001D38:	// 4001d38: <22730010>	ADDI      S3 = S3 + 0010
	state.r[S3] = state.r[S3] + 0x0010;


_04001D3C:	// 4001d3c: <22520010>	ADDI      S2 = S2 + 0010
	state.r[S2] = state.r[S2] + 0x0010;


_04001D40:	// 4001d40: <022f8820>	ADD       S1 = S1+T7
	state.r[S1] = (state.r[S1] + state.r[T7]);


_04001D44:	// 4001d44: <020f8020>	ADD       S0 = S0+T7
	state.r[S0] = (state.r[S0] + state.r[T7]);


_04001D48:	// 4001d48: <4b58ad54>	VADDC	vec21 = vec21 + vec24[2]
	{
		_u16		flag0 = 0;
		_u16		s2value = state.v[24].U16[5];
		VADDC_operation(0, state.v[21].U16[0], state.v[21].U16[0], s2value, 1, 0, 0, 1)
		VADDC_operation(1, state.v[21].U16[1], state.v[21].U16[1], s2value, 1, 0, 0, 1)
		VADDC_operation(2, state.v[21].U16[2], state.v[21].U16[2], s2value, 1, 0, 0, 1)
		VADDC_operation(3, state.v[21].U16[3], state.v[21].U16[3], s2value, 1, 0, 0, 1)
		VADDC_operation(4, state.v[21].U16[4], state.v[21].U16[4], s2value, 1, 0, 0, 1)
		VADDC_operation(5, state.v[21].U16[5], state.v[21].U16[5], s2value, 1, 0, 0, 1)
		VADDC_operation(6, state.v[21].U16[6], state.v[21].U16[6], s2value, 1, 0, 0, 1)
		VADDC_operation(7, state.v[21].U16[7], state.v[21].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = flag0;
	}


_04001D4C:	// 4001d4c: <4b38a510>	VADD      vec20 = vec20 + vec24[1]
	{
		_u16		flag0 = state.flag[0];
		_u16		s2value = state.v[24].U16[6];
		VADD_operation(0, state.v[20].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VADD_operation(1, state.v[20].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VADD_operation(2, state.v[20].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VADD_operation(3, state.v[20].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VADD_operation(4, state.v[20].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VADD_operation(5, state.v[20].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VADD_operation(6, state.v[20].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VADD_operation(7, state.v[20].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


_04001D50:	// 4001d50: <1ea00008>	BGTZ      (R0>0) --> 1d74
	sp_reg_pc = 0x04001D50;
	if((_s32)state.r[S5] > 0)
	{
		{
			_u32 addr = (0x00000000 + state.r[T5]);
			int shifter = ((addr & 0xf) << 3);

			if (shifter == 0 && (addr&3) == 0 )
			{
				addr &= 0xfff;
				state.v[17].U32[0] = *(_u32 *)&pDMEM[addr+12];
				state.v[17].U32[1] = *(_u32 *)&pDMEM[addr+8];
				state.v[17].U32[2] = *(_u32 *)&pDMEM[addr+4];
				state.v[17].U32[3] = *(_u32 *)&pDMEM[addr];
			}
			else
			{
				_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
				_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
				_u64		value1 = Load64_DMEM(addr+8);
				_u64		value2 = Load64_DMEM(addr);
				if (shifter > 0x40)
				{
					temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
					temp1 = 0;
				} else {
					temp1 = ((temp1 >> shifter) << shifter);
				}
				value1 = value1 & temp1;
				value2 = value2 & temp2;

				state.v[17].U64[0] = state.v[17].U64[0] & ~temp1;
				state.v[17].U64[1] = state.v[17].U64[1] & ~temp2;
				state.v[17].U64[0] = state.v[17].U64[0] | value1;
				state.v[17].U64[1] = state.v[17].U64[1] | value2;
			}
		}
		goto _04001D74;
	}


_04001D54:	// 4001d54: <c9b12000>	LQV       vec17 <00> = [T5 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[T5]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[17].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[17].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[17].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[17].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[17].U64[0] = state.v[17].U64[0] & ~temp1;
			state.v[17].U64[1] = state.v[17].U64[1] & ~temp2;
			state.v[17].U64[0] = state.v[17].U64[0] | value1;
			state.v[17].U64[1] = state.v[17].U64[1] | value2;
		}
	}


_04001D58:	// 4001d58: <4b18a523>	VGE       vec20 = (vec20 >= vec24[0])
	rsp_cop2_vge_element(&state.v[20], &state.v[20], &state.v[24].U16[7]);


_04001D5C:	// 4001d5c: <4bb89cd4>	VADDC	vec19 = vec19 + vec24[5]
	{
		_u16		flag0 = 0;
		_u16		s2value = state.v[24].U16[2];
		VADDC_operation(0, state.v[19].U16[0], state.v[19].U16[0], s2value, 1, 0, 0, 1)
		VADDC_operation(1, state.v[19].U16[1], state.v[19].U16[1], s2value, 1, 0, 0, 1)
		VADDC_operation(2, state.v[19].U16[2], state.v[19].U16[2], s2value, 1, 0, 0, 1)
		VADDC_operation(3, state.v[19].U16[3], state.v[19].U16[3], s2value, 1, 0, 0, 1)
		VADDC_operation(4, state.v[19].U16[4], state.v[19].U16[4], s2value, 1, 0, 0, 1)
		VADDC_operation(5, state.v[19].U16[5], state.v[19].U16[5], s2value, 1, 0, 0, 1)
		VADDC_operation(6, state.v[19].U16[6], state.v[19].U16[6], s2value, 1, 0, 0, 1)
		VADDC_operation(7, state.v[19].U16[7], state.v[19].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = flag0;
	}


_04001D60:	// 4001d60: <ca7d2000>	LQV       vec29 <00> = [S3 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S3]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[29].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[29].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[29].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[29].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[29].U64[0] = state.v[29].U64[0] & ~temp1;
			state.v[29].U64[1] = state.v[29].U64[1] & ~temp2;
			state.v[29].U64[0] = state.v[29].U64[0] | value1;
			state.v[29].U64[1] = state.v[29].U64[1] | value2;
		}
	}


_04001D64:	// 4001d64: <4b989490>	VADD      vec18 = vec18 + vec24[4]
	{
		_u16		flag0 = state.flag[0];
		_u16		s2value = state.v[24].U16[3];
		VADD_operation(0, state.v[18].U16[0], state.v[18].U16[0], s2value, 1, 0, 0, 1)
		VADD_operation(1, state.v[18].U16[1], state.v[18].U16[1], s2value, 1, 0, 0, 1)
		VADD_operation(2, state.v[18].U16[2], state.v[18].U16[2], s2value, 1, 0, 0, 1)
		VADD_operation(3, state.v[18].U16[3], state.v[18].U16[3], s2value, 1, 0, 0, 1)
		VADD_operation(4, state.v[18].U16[4], state.v[18].U16[4], s2value, 1, 0, 0, 1)
		VADD_operation(5, state.v[18].U16[5], state.v[18].U16[5], s2value, 1, 0, 0, 1)
		VADD_operation(6, state.v[18].U16[6], state.v[18].U16[6], s2value, 1, 0, 0, 1)
		VADD_operation(7, state.v[18].U16[7], state.v[18].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


_04001D68:	// 4001d68: <ca3b2000>	LQV       vec27 <00> = [S1 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}


_04001D6C:	// 4001d6c: <09000762>	J         04001d88
	goto _04001D88;


_04001D70:	// 4001d70: <00000000>	NOP       


_04001D74:	// 4001d74: <4b18a524>	VCL ?-?

	// [start function: DKR1D74_1D84]

	DKR1D74_1D84();
	goto _04001D88;

_04001D78:	// 4001d78: <4bb89cd4>	VADDC	vec19 = vec19 + vec24[5]

_04001D7C:	// 4001d7c: <ca7d2000>	LQV       vec29 <00> = [S3 + 0x00]

_04001D80:	// 4001d80: <4b989490>	VADD      vec18 = vec18 + vec24[4]

_04001D84:	// 4001d84: <ca3b2000>	LQV       vec27 <00> = [S1 + 0x00]
	ErrorToCallFunction(0x04001D84);

	// [end of function: DKR1D74_1D84]

_04001D88:	// 4001d88: <4bd8a400>	VMULF     vec16 = ( acc = (vec20 * vec24[6]) << 1 ) >> 16

	// [start function: DKR1D88_1E0C]

	DKR1D88_1E0C();
	goto _04001E10;

_04001D8C:	// 4001d8c: <eaf42000>	SQV       [S7 + 0x00] = vec20 <00>

_04001D90:	// 4001d90: <4bf8a3c0>	VMULF     vec15 = ( acc = (vec20 * vec24[7]) << 1 ) >> 16

_04001D94:	// 4001d94: <eaf52001>	SQV       [S7 + 0x10] = vec21 <00>

_04001D98:	// 4001d98: <4bcaef40>	VMULF     vec29 = ( acc = (vec29 * vec10[6]) << 1 ) >> 16

_04001D9C:	// 4001d9c: <4a108f48>	VMACF     vec29 = ( acc += (vec17 * vec16[<none>]) << 1 ) >> 16

_04001DA0:	// 4001da0: <ca5c2000>	LQV       vec28 <00> = [S2 + 0x00]

_04001DA4:	// 4001da4: <4bcadec0>	VMULF     vec27 = ( acc = (vec27 * vec10[6]) << 1 ) >> 16

_04001DA8:	// 4001da8: <ca1a2000>	LQV       vec26 <00> = [S0 + 0x00]

_04001DAC:	// 4001dac: <4a0f8ec8>	VMACF     vec27 = ( acc += (vec17 * vec15[<none>]) << 1 ) >> 16

_04001DB0:	// 4001db0: <1e800007>	BGTZ      (R0>0) --> 1dd0

_04001DB4:	// 4001db4: <ea7d2000>	SQV       [S3 + 0x00] = vec29 <00>

_04001DB8:	// 4001db8: <4b7894a3>	VGE       vec18 = (vec18 >= vec24[3])

_04001DBC:	// 4001dbc: <4b58ad54>	VADDC	vec21 = vec21 + vec24[2]

_04001DC0:	// 4001dc0: <ea3b2000>	SQV       [S1 + 0x00] = vec27 <00>

_04001DC4:	// 4001dc4: <4b38a510>	VADD      vec20 = vec20 + vec24[1]

_04001DC8:	// 4001dc8: <09000778>	J         04001de0

_04001DCC:	// 4001dcc: <00000000>	NOP       

_04001DD0:	// 4001dd0: <4b7894a4>	VCL ?-?

_04001DD4:	// 4001dd4: <4b58ad54>	VADDC	vec21 = vec21 + vec24[2]

_04001DD8:	// 4001dd8: <ea3b2000>	SQV       [S1 + 0x00] = vec27 <00>

_04001DDC:	// 4001ddc: <4b38a510>	VADD      vec20 = vec20 + vec24[1]

_04001DE0:	// 4001de0: <4bd89400>	VMULF     vec16 = ( acc = (vec18 * vec24[6]) << 1 ) >> 16

_04001DE4:	// 4001de4: <21cefff0>	ADDI      T6 = T6 + fff0

_04001DE8:	// 4001de8: <4bf893c0>	VMULF     vec15 = ( acc = (vec18 * vec24[7]) << 1 ) >> 16

_04001DEC:	// 4001dec: <22730010>	ADDI      S3 = S3 + 0010

_04001DF0:	// 4001df0: <4bcae700>	VMULF     vec28 = ( acc = (vec28 * vec10[6]) << 1 ) >> 16

_04001DF4:	// 4001df4: <022f8820>	ADD       S1 = S1+T7

_04001DF8:	// 4001df8: <4a108f08>	VMACF     vec28 = ( acc += (vec17 * vec16[<none>]) << 1 ) >> 16

_04001DFC:	// 4001dfc: <21ad0010>	ADDI      T5 = T5 + 0010

_04001E00:	// 4001e00: <4bcad680>	VMULF     vec26 = ( acc = (vec26 * vec10[6]) << 1 ) >> 16

_04001E04:	// 4001e04: <4a0f8e88>	VMACF     vec26 = ( acc += (vec17 * vec15[<none>]) << 1 ) >> 16

_04001E08:	// 4001e08: <ea5c2000>	SQV       [S2 + 0x00] = vec28 <00>

_04001E0C:	// 4001e0c: <22520010>	ADDI      S2 = S2 + 0010
	ErrorToCallFunction(0x04001E0C);

	// [end of function: DKR1D88_1E0C]

_04001E10:	// 4001e10: <19c00003>	BLEZ      (R0<=0) --> 1e20
	sp_reg_pc = 0x04001E10;
	if ((_s32)state.r[T6] <= 0)
	{
		{
			_u32    addr = (0x00000000 + state.r[S0]);
			int     shifter = ((addr & 0xf) << 3);

			if (shifter == 0 && (addr&3) == 0 )
			{
				addr &= 0xfff;
				*(_u32 *)&pDMEM[addr+12] = state.v[26].U32[0];
				*(_u32 *)&pDMEM[addr+8 ] = state.v[26].U32[1];
				*(_u32 *)&pDMEM[addr+4 ] = state.v[26].U32[2];
				*(_u32 *)&pDMEM[addr   ] = state.v[26].U32[3];
			}
			else
			{
				_u64    value1 = Load64_DMEM(addr+8);
				_u64    value2 = Load64_DMEM(addr);
				_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
				_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

				if (shifter > 0x40)
				{
					temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
					temp1 = 0;
				} else {
					temp1 = ((temp1 >> shifter) << shifter);
				}
				value1 = value1 & ~temp1;
				value2 = value2 & ~temp2;

				value1 |= (state.v[26].U64[0] & temp1);
				value2 |= (state.v[26].U64[1] & temp2);

				Save64_DMEM(value1, addr+8);
				Save64_DMEM(value2, addr  );
			}
		}
		goto _04001E20;
	}


_04001E14:	// 4001e14: <ea1a2000>	SQV       [S0 + 0x00] = vec26 <00>
	{
		_u32    addr = (0x00000000 + state.r[S0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[26].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[26].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[26].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[26].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[26].U64[0] & temp1);
			value2 |= (state.v[26].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001E18:	// 4001e18: <09000754>	J         04001d50
	state.r[S0] = (state.r[S0] + state.r[T7]);
	goto _04001D50;


_04001E1C:	// 4001e1c: <020f8020>	ADD       S0 = S0+T7
	state.r[S0] = (state.r[S0] + state.r[T7]);


_04001E20:	// 4001e20: <eaf22002>	SQV       [S7 + 0x20] = vec18 <00>
	{
		_u32    addr = (0x00000020 + state.r[S7]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[18].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[18].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[18].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[18].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[18].U64[0] & temp1);
			value2 |= (state.v[18].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001E24:	// 4001e24: <eaf32003>	SQV       [S7 + 0x30] = vec19 <00>
	{
		_u32    addr = (0x00000030 + state.r[S7]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[19].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[19].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[19].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[19].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[19].U64[0] & temp1);
			value2 |= (state.v[19].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001E28:	// 4001e28: <eaf82004>	SQV       [S7 + 0x40] = vec24 <00>
	{
		_u32    addr = (0x00000040 + state.r[S7]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[24].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[24].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[24].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[24].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[24].U64[0] & temp1);
			value2 |= (state.v[24].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001E2C:	// 4001e2c: <0d000470>	JAL	    040011c0
	state.r[V1] = 0 + 0x004F;
	sp_reg_pc = 0x04001E2C;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _040011C0;


_04001E30:	// 4001e30: <2003004f>	ADDI      V1 = R0 + 004f
	state.r[V1] = 0 + 0x004F;


_04001E34:	// 4001e34: <09000446>	J         04001118
	goto _04001118;


_04001E38:	// 4001e38: <00000000>	NOP       


_04001E3C:	// 4001e3c: <c81f2000>	LQV       vec31 <00> = [R0 + 0x00]

	// [start function: DKR1E3C_1F30]

	DKR1E3C_1F30();
	goto _04001F34;

_04001E40:	// 4001e40: <97120004>	LHU       S2 = [T8+0004]

_04001E44:	// 4001e44: <1240003b>	BEQ       (R0==S2) --> 1f34

_04001E48:	// 4001e48: <00000000>	NOP       

_04001E4C:	// 4001e4c: <3322ffff>	ANDI      V0 = T9 & ffff

_04001E50:	// 4001e50: <204205c0>	ADDI      V0 = V0 + 05c0

_04001E54:	// 4001e54: <00190c02>	SRL       AT = T9 >> 16

_04001E58:	// 4001e58: <202105c0>	ADDI      AT = AT + 05c0

_04001E5C:	// 4001e5c: <3351ffff>	ANDI      S1 = K0 & ffff

_04001E60:	// 4001e60: <4891f000>	MTC2      vec30 <00> = S1

_04001E64:	// 4001e64: <12c00005>	BEQ       (R0==S6) --> 1e7c

_04001E68:	// 4001e68: <00000000>	NOP       

_04001E6C:	// 4001e6c: <40033000>	MFC0      A2 = SP write DMA length

_04001E70:	// 4001e70: <1460fffe>	BNE       (R0!=V1) --> 1e6c

_04001E74:	// 4001e74: <00000000>	NOP       

_04001E78:	// 4001e78: <0000b020>	ADD       S6 = R0+R0

_04001E7C:	// 4001e7c: <c8592000>	LQV       vec25 <00> = [V0 + 0x00]

_04001E80:	// 4001e80: <c83d2000>	LQV       vec29 <00> = [AT + 0x00]

_04001E84:	// 4001e84: <c8582001>	LQV       vec24 <00> = [V0 + 0x10]

_04001E88:	// 4001e88: <c83c2001>	LQV       vec28 <00> = [AT + 0x10]

_04001E8C:	// 4001e8c: <4bdfce40>	VMULF     vec25 = ( acc = (vec25 * vec31[6]) << 1 ) >> 16

_04001E90:	// 4001e90: <c83b2002>	LQV       vec27 <00> = [AT + 0x20]

_04001E94:	// 4001e94: <c8572002>	LQV       vec23 <00> = [V0 + 0x20]

_04001E98:	// 4001e98: <4b1eee48>	VMACF     vec25 = ( acc += (vec29 * vec30[0]) << 1 ) >> 16

_04001E9C:	// 4001e9c: <2252ffe0>	ADDI      S2 = S2 + ffe0

_04001EA0:	// 4001ea0: <4bdfc600>	VMULF     vec24 = ( acc = (vec24 * vec31[6]) << 1 ) >> 16

_04001EA4:	// 4001ea4: <c83a2003>	LQV       vec26 <00> = [AT + 0x30]

_04001EA8:	// 4001ea8: <c8562003>	LQV       vec22 <00> = [V0 + 0x30]

_04001EAC:	// 4001eac: <20210040>	ADDI      AT = AT + 0040

_04001EB0:	// 4001eb0: <20420040>	ADDI      V0 = V0 + 0040

_04001EB4:	// 4001eb4: <4b1ee608>	VMACF     vec24 = ( acc += (vec28 * vec30[0]) << 1 ) >> 16

_04001EB8:	// 4001eb8: <1a40001c>	BLEZ      (R0<=0) --> 1f2c

_04001EBC:	// 4001ebc: <00000000>	NOP       

_04001EC0:	// 4001ec0: <4bdfbdc0>	VMULF     vec23 = ( acc = (vec23 * vec31[6]) << 1 ) >> 16

_04001EC4:	// 4001ec4: <e859207c>	SQV       [V0 + 0xc0] = vec25 <00>

_04001EC8:	// 4001ec8: <c83d2000>	LQV       vec29 <00> = [AT + 0x00]

_04001ECC:	// 4001ecc: <c8592000>	LQV       vec25 <00> = [V0 + 0x00]

_04001ED0:	// 4001ed0: <4b1eddc8>	VMACF     vec23 = ( acc += (vec27 * vec30[0]) << 1 ) >> 16

_04001ED4:	// 4001ed4: <4bdfb580>	VMULF     vec22 = ( acc = (vec22 * vec31[6]) << 1 ) >> 16

_04001ED8:	// 4001ed8: <e858207d>	SQV       [V0 + 0xd0] = vec24 <00>

_04001EDC:	// 4001edc: <c83c2001>	LQV       vec28 <00> = [AT + 0x10]

_04001EE0:	// 4001ee0: <c8582001>	LQV       vec24 <00> = [V0 + 0x10]

_04001EE4:	// 4001ee4: <4b1ed588>	VMACF     vec22 = ( acc += (vec26 * vec30[0]) << 1 ) >> 16

_04001EE8:	// 4001ee8: <20210040>	ADDI      AT = AT + 0040

_04001EEC:	// 4001eec: <4bdfce40>	VMULF     vec25 = ( acc = (vec25 * vec31[6]) << 1 ) >> 16

_04001EF0:	// 4001ef0: <e857207e>	SQV       [V0 + 0xe0] = vec23 <00>

_04001EF4:	// 4001ef4: <c83b207e>	LQV       vec27 <00> = [AT + 0xe0]

_04001EF8:	// 4001ef8: <c8572002>	LQV       vec23 <00> = [V0 + 0x20]

_04001EFC:	// 4001efc: <4b1eee48>	VMACF     vec25 = ( acc += (vec29 * vec30[0]) << 1 ) >> 16

_04001F00:	// 4001f00: <2252ffc0>	ADDI      S2 = S2 + ffc0

_04001F04:	// 4001f04: <4bdfc600>	VMULF     vec24 = ( acc = (vec24 * vec31[6]) << 1 ) >> 16

_04001F08:	// 4001f08: <e856207f>	SQV       [V0 + 0xf0] = vec22 <00>

_04001F0C:	// 4001f0c: <c83a207f>	LQV       vec26 <00> = [AT + 0xf0]

_04001F10:	// 4001f10: <c8562003>	LQV       vec22 <00> = [V0 + 0x30]

_04001F14:	// 4001f14: <4b1ee608>	VMACF     vec24 = ( acc += (vec28 * vec30[0]) << 1 ) >> 16

_04001F18:	// 4001f18: <1e40ffe9>	BGTZ      (R0>0) --> 1ec0

_04001F1C:	// 4001f1c: <20420040>	ADDI      V0 = V0 + 0040

_04001F20:	// 4001f20: <22520020>	ADDI      S2 = S2 + 0020

_04001F24:	// 4001f24: <1a400003>	BLEZ      (R0<=0) --> 1f34

_04001F28:	// 4001f28: <00000000>	NOP       

_04001F2C:	// 4001f2c: <e859207c>	SQV       [V0 + 0xc0] = vec25 <00>

_04001F30:	// 4001f30: <e858207d>	SQV       [V0 + 0xd0] = vec24 <00>
	ErrorToCallFunction(0x04001F30);

	// [end of function: DKR1E3C_1F30]

_04001F34:	// 4001f34: <09000446>	J         04001118
	goto _04001118;


_04001F38:	// 4001f38: <00000000>	NOP       


_04001F3C:	// 4001f3c: <00000000>	NOP       


_04001F40:	// 4001f40: <34210001>	ORI       AT = AT | 0x0001
	state.r[AT] = (state.r[AT] | 0x00000001);


_04001F44:	// 4001f44: <0900041a>	J         04001068
	state.r[AT] = 0 + 0x0FC0;
	goto _04001068;


_04001F48:	// 4001f48: <20010fc0>	ADDI      AT = R0 + 0fc0
	state.r[AT] = 0 + 0x0FC0;


_04001F4C:	// 4001f4c: <8c220010>	LW        V0 = [AT+0010]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000010) & 0xfff);


_04001F50:	// 4001f50: <20030f7f>	ADDI      V1 = R0 + 0f7f
	state.r[V1] = 0 + 0x0F7F;


_04001F54:	// 4001f54: <20071080>	ADDI      A3 = R0 + 1080
	state.r[A3] = 0 + 0x1080;


_04001F58:	// 4001f58: <40870000>	MTC0      SP memory address = A3
	DMEM_Address = state.r[A3];


_04001F5C:	// 4001f5c: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_04001F60:	// 4001f60: <40831000>	MTC0      SP read DMA length = V1
	sp_reg_pc = 0x04001F60;
	DMARead(state.r[V1]);


_04001F64:	// 4001f64: <40043000>	MFC0      A2 = SP status
	state.r[A0] = 0;


_04001F68:	// 4001f68: <1480fffe>	BNE       (R0!=A0) --> 1f64
	sp_reg_pc = 0x04001F68;
	if (state.r[A0] != 0)
	{
		goto _04001F64;
	}


_04001F6C:	// 4001f6c: <00000000>	NOP       


_04001F70:	// 4001f70: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x04001F70;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_04001F74:	// 4001f74: <00000000>	NOP       


_04001F78:	// 4001f78: <00e00008>	JR        A3
	{
		_u32	temp = ((state.r[A3] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_04001F7C:	// 4001f7c: <40803800>	MTC0      SP semaphore = R0


_04001F80:	// 4001f80: <40082000>	MFC0      A0 = DP CMD DMA start
	state.r[T0] = 0;


_04001F84:	// 4001f84: <31080080>	ANDI      T0 = T0 & 0080
	state.r[T0] = (state.r[T0] & 0x00000080);


_04001F88:	// 4001f88: <15000002>	BNE       (R0!=T0) --> 1f94
	sp_reg_pc = 0x04001F88;
	if (state.r[T0] != 0)
	{
		goto _04001F94;
	}


_04001F8C:	// 4001f8c: <00000000>	NOP       


_04001F90:	// 4001f90: <03e00008>	JR        RA
	{
		_u32	temp = ((state.r[RA] & 0x0FFF) >> 2);
		_u32	tempAddr = JumpTable[temp];
		__asm mov eax, tempAddr;
		__asm jmp eax;
	}


_04001F94:	// 4001f94: <40803800>	MTC0      SP semaphore = R0


_04001F98:	// 4001f98: <34085200>	ORI       T0 = R0 | 0x5200
	state.r[T0] = (0 | 0x00005200);


_04001F9C:	// 4001f9c: <40882000>	MTC0      SP status = T0


_04001FA0:	// 4001fa0: <0000000d>	BREAK
	state.halt = 1;
	return;


_04001FA4:	// 4001fa4: <00000000>	NOP       


_04001FA8:	// 4001fa8: <8c220004>	LW        V0 = [AT+0004]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000004) & 0xfff);


_04001FAC:	// 4001fac: <30420002>	ANDI      V0 = V0 & 0002
	state.r[V0] = (state.r[V0] & 0x00000002);


_04001FB0:	// 4001fb0: <10400007>	BEQ       (R0==V0) --> 1fd0
	sp_reg_pc = 0x04001FB0;
	if (state.r[V0] == 0)
	{
		goto _04001FD0;
	}


_04001FB4:	// 4001fb4: <00000000>	NOP       


_04001FB8:	// 4001fb8: <0d000410>	JAL	    04001040
	sp_reg_pc = 0x04001FB8;
	state.r[RA] = (sp_reg_pc + 8) & 0x1fff;
	goto _04001040;


_04001FBC:	// 4001fbc: <00000000>	NOP       


_04001FC0:	// 4001fc0: <40025800>	MFC0      T3 = SP read DMA length
	state.r[V0] = 0;


_04001FC4:	// 4001fc4: <30420100>	ANDI      V0 = V0 & 0100
	state.r[V0] = (state.r[V0] & 0x00000100);


_04001FC8:	// 4001fc8: <1c40ffed>	BGTZ      (R0>0) --> 1f80
	sp_reg_pc = 0x04001FC8;
	if((_s32)state.r[V0] > 0)
	{
		goto _04001F80;
	}


_04001FCC:	// 4001fcc: <00000000>	NOP       


_04001FD0:	// 4001fd0: <8c220018>	LW        V0 = [AT+0018]
	state.r[V0] = (_s32)Load32_DMEM((state.r[AT] + 0x00000018) & 0xfff);


_04001FD4:	// 4001fd4: <8c23001c>	LW        V1 = [AT+001c]
	state.r[V1] = (_s32)Load32_DMEM((state.r[AT] + 0x0000001C) & 0xfff);


_04001FD8:	// 4001fd8: <2063ffff>	ADDI      V1 = V1 + ffff
	state.r[V1] = state.r[V1] + 0xFFFFFFFF;


_04001FDC:	// 4001fdc: <401e2800>	MFC0      A1 = unknown
	state.r[S8] = 0;


_04001FE0:	// 4001fe0: <17c0fffe>	BNE       (R0!=S8) --> 1fdc
	sp_reg_pc = 0x04001FE0;
	if (state.r[S8] != 0)
	{
		goto _04001FDC;
	}


_04001FE4:	// 4001fe4: <00000000>	NOP       


_04001FE8:	// 4001fe8: <40800000>	MTC0      SP memory address = R0
	DMEM_Address = 0;


_04001FEC:	// 4001fec: <40820800>	MTC0      SP DRAM DMA address = V0
	RDRAM_Address = (state.r[V0] & 0xFFFFFF);


_04001FF0:	// 4001ff0: <40831000>	MTC0      SP read DMA length = V1
	sp_reg_pc = 0x04001FF0;
	DMARead(state.r[V1]);


_04001FF4:	// 4001ff4: <40043000>	MFC0      A2 = SP status
	state.r[A0] = 0;


_04001FF8:	// 4001ff8: <1480fffe>	BNE       (R0!=A0) --> 1ff4
	sp_reg_pc = 0x04001FF8;
	if (state.r[A0] != 0)
	{
		goto _04001FF4;
	}


_04001FFC:	// 4001ffc: <00000000>	NOP       

	state.halt = 1;
	return;

	_BuildJumpTable:
	#include "jumptable.h"
	goto _Label;
}

void DKR1458_1474(void)
{

_04001458:	// 4001458: <c8211800>	LDV       vec01 <00> = [AT + 0x00]
	rsp_ldv_compiler((state.r[AT] & 0xFFF), 1, 8);


_0400145C:	// 400145c: <c8221801>	LDV       vec02 <00> = [AT + 0x08]
	rsp_ldv_compiler((state.r[AT] + 0x00000008) & 0xFFF, 2, 8);


_04001460:	// 4001460: <2063fff0>	ADDI      V1 = V1 + fff0
	state.r[V1] = state.r[V1] + 0xFFFFFFF0;


_04001464:	// 4001464: <20210010>	ADDI      AT = AT + 0010
	state.r[AT] = state.r[AT] + 0x0010;


_04001468:	// 4001468: <e8411800>	SDV       [V0 + 0x00] = vec01 <00>
	{
		_u32	addr = (0x00000000 + state.r[V0]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[1].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[1].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[1].U32[0x00000003];
		}
	}


_0400146C:	// 400146c: <e8421801>	SDV       [V0 + 0x04] = vec02 <00>
	{
		_u32	addr = (0x00000008 + state.r[V0]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[2].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[2].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[2].U32[0x00000003];
		}
	}


_04001470:	// 4001470: <1c60fff9>	BGTZ      (R0>0) --> 1458
	sp_reg_pc = 0x04001470;
	if((_s32)state.r[V1] > 0)
	{
		state.r[V0] = state.r[V0] + 0x0010;
		goto _04001458;
	}


_04001474:	// 4001474: <20420010>	ADDI      V0 = V0 + 0010
	state.r[V0] = state.r[V0] + 0x0010;

_04001478:
	;
}

void DKR1864_18B0(void)
{

	// 4001864: <4bdccc07>	VMUDH     vec16 = ( acc = (vec25 * vec28[6]) << 16) >> 16
	{
		_u16		s2value = state.v[28].U16[1];
		VMUDH_operation(0, state.v[16].U16[0], state.v[25].U16[0], s2value, 0, 1, 0, 1)
		VMUDH_operation(1, state.v[16].U16[1], state.v[25].U16[1], s2value, 0, 1, 0, 1)
		VMUDH_operation(2, state.v[16].U16[2], state.v[25].U16[2], s2value, 0, 1, 0, 1)
		VMUDH_operation(3, state.v[16].U16[3], state.v[25].U16[3], s2value, 0, 1, 0, 1)
		VMUDH_operation(4, state.v[16].U16[4], state.v[25].U16[4], s2value, 0, 1, 0, 1)
		VMUDH_operation(5, state.v[16].U16[5], state.v[25].U16[5], s2value, 0, 1, 0, 1)
		VMUDH_operation(6, state.v[16].U16[6], state.v[25].U16[6], s2value, 0, 1, 0, 1)
		VMUDH_operation(7, state.v[16].U16[7], state.v[25].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001868: <22b50010>	ADDI      S5 = S5 + 0010
	state.r[S5] = state.r[S5] + 0x0010;


	// 400186c: <4bfcc40f>	VMADH     vec16 = ( acc+= (vec24 * vec28[7]) << 16) >> 16
	{
		_u16		s2value = state.v[28].U16[0];
		VMADH_operation(0, state.v[16].U16[0], state.v[24].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[24].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[24].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[24].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[24].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[24].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[24].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[24].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001870: <2273fff0>	ADDI      S3 = S3 + fff0
	state.r[S3] = state.r[S3] + 0xFFFFFFF0;


	// 4001874: <4b1ebc0f>	VMADH     vec16 = ( acc+= (vec23 * vec30[0]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMADH_operation(0, state.v[16].U16[0], state.v[23].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[23].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[23].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[23].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[23].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[23].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[23].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[23].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001878: <4b3eb40f>	VMADH     vec16 = ( acc+= (vec22 * vec30[1]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[6];
		VMADH_operation(0, state.v[16].U16[0], state.v[22].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[22].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[22].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[22].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[22].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[22].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[22].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[22].U16[7], s2value, 0, 1, 0, 1)
	}


	// 400187c: <4b5eac0f>	VMADH     vec16 = ( acc+= (vec21 * vec30[2]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[5];
		VMADH_operation(0, state.v[16].U16[0], state.v[21].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[21].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[21].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[21].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[21].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[21].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[21].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[21].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001880: <4b7ea40f>	VMADH     vec16 = ( acc+= (vec20 * vec30[3]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[4];
		VMADH_operation(0, state.v[16].U16[0], state.v[20].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[20].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[20].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[20].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[20].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[20].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[20].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[20].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001884: <4b9e9f0f>	VMADH     vec28 = ( acc+= (vec19 * vec30[4]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[3];
		VMADH_operation(0, state.v[28].U16[0], state.v[19].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[28].U16[1], state.v[19].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[28].U16[2], state.v[19].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[28].U16[3], state.v[19].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[28].U16[4], state.v[19].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[28].U16[5], state.v[19].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[28].U16[6], state.v[19].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[28].U16[7], state.v[19].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001888: <4bbe940f>	VMADH     vec16 = ( acc+= (vec18 * vec30[5]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[2];
		VMADH_operation(0, state.v[16].U16[0], state.v[18].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[18].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[18].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[18].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[18].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[18].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[18].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[18].U16[7], s2value, 0, 1, 0, 1)
	}


	// 400188c: <4bde8c0f>	VMADH     vec16 = ( acc+= (vec17 * vec30[6]) << 16) >> 16
	{
		_u16		s2value = state.v[30].U16[1];
		VMADH_operation(0, state.v[16].U16[0], state.v[17].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[17].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[17].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[17].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[17].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[17].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[17].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[17].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001890: <4bbff40f>	VMADH     vec16 = ( acc+= (vec30 * vec31[5]) << 16) >> 16
	{
		_u16		s2value = state.v[31].U16[2];
		VMADH_operation(0, state.v[16].U16[0], state.v[30].U16[0], s2value, 0, 1, 0, 1)
		VMADH_operation(1, state.v[16].U16[1], state.v[30].U16[1], s2value, 0, 1, 0, 1)
		VMADH_operation(2, state.v[16].U16[2], state.v[30].U16[2], s2value, 0, 1, 0, 1)
		VMADH_operation(3, state.v[16].U16[3], state.v[30].U16[3], s2value, 0, 1, 0, 1)
		VMADH_operation(4, state.v[16].U16[4], state.v[30].U16[4], s2value, 0, 1, 0, 1)
		VMADH_operation(5, state.v[16].U16[5], state.v[30].U16[5], s2value, 0, 1, 0, 1)
		VMADH_operation(6, state.v[16].U16[6], state.v[30].U16[6], s2value, 0, 1, 0, 1)
		VMADH_operation(7, state.v[16].U16[7], state.v[30].U16[7], s2value, 0, 1, 0, 1)
	}


	// 4001894: <cabe1800>	LDV       vec30 <00> = [S5 + 0x00]
	rsp_ldv_compiler((state.r[S5] & 0xFFF), 30, 8);


	// 4001898: <4b3c7e9d>	VSAW $v26, $v15, $v28[[1]]
	state.v[26].U16[0] = state.accum[0].U16[2];
	state.v[26].U16[1] = state.accum[1].U16[2];
	state.v[26].U16[2] = state.accum[2].U16[2];
	state.v[26].U16[3] = state.accum[3].U16[2];
	state.v[26].U16[4] = state.accum[4].U16[2];
	state.v[26].U16[5] = state.accum[5].U16[2];
	state.v[26].U16[6] = state.accum[6].U16[2];
	state.v[26].U16[7] = state.accum[7].U16[2];


	// 400189c: <cabe1c01>	LDV       vec30 <08> = [S5 + 0x08]
	rsp_ldv_compiler((state.r[S5] + 0x00000008) & 0xFFF, 30, 0);


	// 40018a0: <4b1c7f1d>	VSAW $v28, $v15, $v28[[0]]
	state.v[28].U16[0] = state.accum[0].U16[3];
	state.v[28].U16[1] = state.accum[1].U16[3];
	state.v[28].U16[2] = state.accum[2].U16[3];
	state.v[28].U16[3] = state.accum[3].U16[3];
	state.v[28].U16[4] = state.accum[4].U16[3];
	state.v[28].U16[5] = state.accum[5].U16[3];
	state.v[28].U16[6] = state.accum[6].U16[3];
	state.v[28].U16[7] = state.accum[7].U16[3];


	// 40018a4: <4b0ed406>	VMUDN     vec16 = ( acc = vec26 * vec14[0]      ) >> 16
	{
		_u16		s2value = state.v[14].U16[7];
		VMUDN_operation(0, state.v[16].U16[0], state.v[26].U16[0], s2value, 1, 1, 1, 1)
		VMUDN_operation(1, state.v[16].U16[1], state.v[26].U16[1], s2value, 1, 1, 1, 1)
		VMUDN_operation(2, state.v[16].U16[2], state.v[26].U16[2], s2value, 1, 1, 1, 1)
		VMUDN_operation(3, state.v[16].U16[3], state.v[26].U16[3], s2value, 1, 1, 1, 1)
		VMUDN_operation(4, state.v[16].U16[4], state.v[26].U16[4], s2value, 1, 1, 1, 1)
		VMUDN_operation(5, state.v[16].U16[5], state.v[26].U16[5], s2value, 1, 1, 1, 1)
		VMUDN_operation(6, state.v[16].U16[6], state.v[26].U16[6], s2value, 1, 1, 1, 1)
		VMUDN_operation(7, state.v[16].U16[7], state.v[26].U16[7], s2value, 1, 1, 1, 1)
	}


	// 40018a8: <4b0ee70f>	VMADH     vec28 = ( acc+= (vec28 * vec14[0]) << 16) >> 16
	{
		_u16		s2value = state.v[14].U16[7];
		VMADH_operation(0, state.v[28].U16[0], state.v[28].U16[0], s2value, 1, 1, 0, 1)
		VMADH_operation(1, state.v[28].U16[1], state.v[28].U16[1], s2value, 1, 1, 0, 1)
		VMADH_operation(2, state.v[28].U16[2], state.v[28].U16[2], s2value, 1, 1, 0, 1)
		VMADH_operation(3, state.v[28].U16[3], state.v[28].U16[3], s2value, 1, 1, 0, 1)
		VMADH_operation(4, state.v[28].U16[4], state.v[28].U16[4], s2value, 1, 1, 0, 1)
		VMADH_operation(5, state.v[28].U16[5], state.v[28].U16[5], s2value, 1, 1, 0, 1)
		VMADH_operation(6, state.v[28].U16[6], state.v[28].U16[6], s2value, 1, 1, 0, 1)
		VMADH_operation(7, state.v[28].U16[7], state.v[28].U16[7], s2value, 1, 1, 0, 1)
	}


	// 40018ac: <ea9c1800>	SDV       [S4 + 0x00] = vec28 <00>
	{
		_u32	addr = (0x00000000 + state.r[S4]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[28].U64[0x00000001], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[28].U32[0x00000002];
			*(_u32 *)&pDMEM[addr  ] = state.v[28].U32[0x00000003];
		}
	}


	// 40018b0: <ea9c1c01>	SDV       [S4 + 0x04] = vec28 <08>
	{
		_u32	addr = (0x00000008 + state.r[S4]);

		if( addr & 3 )
		{
			Save64_DMEM(state.v[28].U64[0x00000000], addr);
		}
		else
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+4] = state.v[28].U32[0x00000000];
			*(_u32 *)&pDMEM[addr  ] = state.v[28].U32[0x00000001];
		}
	}

_040018B4:
	;
}

void DKR1D74_1D84(void)
{

	// 4001d74: <4b18a524>	VCL ?-?
	rsp_cop2_vcl_element(&state.v[20], &state.v[20], &state.v[24].U16[7]);


	// 4001d78: <4bb89cd4>	VADDC	vec19 = vec19 + vec24[5]
	{
		_u16		flag0 = 0;
		_u16		s2value = state.v[24].U16[2];
		VADDC_operation(0, state.v[19].U16[0], state.v[19].U16[0], s2value, 1, 0, 0, 1)
		VADDC_operation(1, state.v[19].U16[1], state.v[19].U16[1], s2value, 1, 0, 0, 1)
		VADDC_operation(2, state.v[19].U16[2], state.v[19].U16[2], s2value, 1, 0, 0, 1)
		VADDC_operation(3, state.v[19].U16[3], state.v[19].U16[3], s2value, 1, 0, 0, 1)
		VADDC_operation(4, state.v[19].U16[4], state.v[19].U16[4], s2value, 1, 0, 0, 1)
		VADDC_operation(5, state.v[19].U16[5], state.v[19].U16[5], s2value, 1, 0, 0, 1)
		VADDC_operation(6, state.v[19].U16[6], state.v[19].U16[6], s2value, 1, 0, 0, 1)
		VADDC_operation(7, state.v[19].U16[7], state.v[19].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = flag0;
	}


	// 4001d7c: <ca7d2000>	LQV       vec29 <00> = [S3 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S3]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[29].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[29].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[29].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[29].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[29].U64[0] = state.v[29].U64[0] & ~temp1;
			state.v[29].U64[1] = state.v[29].U64[1] & ~temp2;
			state.v[29].U64[0] = state.v[29].U64[0] | value1;
			state.v[29].U64[1] = state.v[29].U64[1] | value2;
		}
	}


	// 4001d80: <4b989490>	VADD      vec18 = vec18 + vec24[4]
	{
		_u16		flag0 = state.flag[0];
		_u16		s2value = state.v[24].U16[3];
		VADD_operation(0, state.v[18].U16[0], state.v[18].U16[0], s2value, 1, 0, 0, 1)
		VADD_operation(1, state.v[18].U16[1], state.v[18].U16[1], s2value, 1, 0, 0, 1)
		VADD_operation(2, state.v[18].U16[2], state.v[18].U16[2], s2value, 1, 0, 0, 1)
		VADD_operation(3, state.v[18].U16[3], state.v[18].U16[3], s2value, 1, 0, 0, 1)
		VADD_operation(4, state.v[18].U16[4], state.v[18].U16[4], s2value, 1, 0, 0, 1)
		VADD_operation(5, state.v[18].U16[5], state.v[18].U16[5], s2value, 1, 0, 0, 1)
		VADD_operation(6, state.v[18].U16[6], state.v[18].U16[6], s2value, 1, 0, 0, 1)
		VADD_operation(7, state.v[18].U16[7], state.v[18].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


	// 4001d84: <ca3b2000>	LQV       vec27 <00> = [S1 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S1]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}

_04001D88:
	;
}

void DKR1D88_1E0C(void)
{

_04001D88:	// 4001d88: <4bd8a400>	VMULF     vec16 = ( acc = (vec20 * vec24[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[1];
		VMULF_operation(0, state.v[16].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[16].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[16].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[16].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[16].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[16].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[16].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[16].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
	}


_04001D8C:	// 4001d8c: <eaf42000>	SQV       [S7 + 0x00] = vec20 <00>
	{
		_u32    addr = (0x00000000 + state.r[S7]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[20].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[20].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[20].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[20].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[20].U64[0] & temp1);
			value2 |= (state.v[20].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001D90:	// 4001d90: <4bf8a3c0>	VMULF     vec15 = ( acc = (vec20 * vec24[7]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[0];
		VMULF_operation(0, state.v[15].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[15].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[15].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[15].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[15].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[15].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[15].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[15].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
	}


_04001D94:	// 4001d94: <eaf52001>	SQV       [S7 + 0x10] = vec21 <00>
	{
		_u32    addr = (0x00000010 + state.r[S7]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[21].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[21].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[21].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[21].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[21].U64[0] & temp1);
			value2 |= (state.v[21].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001D98:	// 4001d98: <4bcaef40>	VMULF     vec29 = ( acc = (vec29 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[29].U16[0], state.v[29].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[29].U16[1], state.v[29].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[29].U16[2], state.v[29].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[29].U16[3], state.v[29].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[29].U16[4], state.v[29].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[29].U16[5], state.v[29].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[29].U16[6], state.v[29].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[29].U16[7], state.v[29].U16[7], s2value, 0, 1, 1, 1)
	}


_04001D9C:	// 4001d9c: <4a108f48>	VMACF     vec29 = ( acc += (vec17 * vec16[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[29].U16[0], state.v[17].U16[0], state.v[16].U16[0], 1, 0, 0, 1)
		VMACF_operation(1, state.v[29].U16[1], state.v[17].U16[1], state.v[16].U16[1], 1, 0, 0, 1)
		VMACF_operation(2, state.v[29].U16[2], state.v[17].U16[2], state.v[16].U16[2], 1, 0, 0, 1)
		VMACF_operation(3, state.v[29].U16[3], state.v[17].U16[3], state.v[16].U16[3], 1, 0, 0, 1)
		VMACF_operation(4, state.v[29].U16[4], state.v[17].U16[4], state.v[16].U16[4], 1, 0, 0, 1)
		VMACF_operation(5, state.v[29].U16[5], state.v[17].U16[5], state.v[16].U16[5], 1, 0, 0, 1)
		VMACF_operation(6, state.v[29].U16[6], state.v[17].U16[6], state.v[16].U16[6], 1, 0, 0, 1)
		VMACF_operation(7, state.v[29].U16[7], state.v[17].U16[7], state.v[16].U16[7], 1, 0, 0, 1)
	}


_04001DA0:	// 4001da0: <ca5c2000>	LQV       vec28 <00> = [S2 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S2]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[28].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[28].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[28].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[28].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[28].U64[0] = state.v[28].U64[0] & ~temp1;
			state.v[28].U64[1] = state.v[28].U64[1] & ~temp2;
			state.v[28].U64[0] = state.v[28].U64[0] | value1;
			state.v[28].U64[1] = state.v[28].U64[1] | value2;
		}
	}


_04001DA4:	// 4001da4: <4bcadec0>	VMULF     vec27 = ( acc = (vec27 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[27].U16[0], state.v[27].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[27].U16[1], state.v[27].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[27].U16[2], state.v[27].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[27].U16[3], state.v[27].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[27].U16[4], state.v[27].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[27].U16[5], state.v[27].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[27].U16[6], state.v[27].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[27].U16[7], state.v[27].U16[7], s2value, 0, 1, 1, 1)
	}


_04001DA8:	// 4001da8: <ca1a2000>	LQV       vec26 <00> = [S0 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[S0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[26].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[26].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[26].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[26].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[26].U64[0] = state.v[26].U64[0] & ~temp1;
			state.v[26].U64[1] = state.v[26].U64[1] & ~temp2;
			state.v[26].U64[0] = state.v[26].U64[0] | value1;
			state.v[26].U64[1] = state.v[26].U64[1] | value2;
		}
	}


_04001DAC:	// 4001dac: <4a0f8ec8>	VMACF     vec27 = ( acc += (vec17 * vec15[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[27].U16[0], state.v[17].U16[0], state.v[15].U16[0], 1, 1, 1, 1)
		VMACF_operation(1, state.v[27].U16[1], state.v[17].U16[1], state.v[15].U16[1], 1, 1, 1, 1)
		VMACF_operation(2, state.v[27].U16[2], state.v[17].U16[2], state.v[15].U16[2], 1, 1, 1, 1)
		VMACF_operation(3, state.v[27].U16[3], state.v[17].U16[3], state.v[15].U16[3], 1, 1, 1, 1)
		VMACF_operation(4, state.v[27].U16[4], state.v[17].U16[4], state.v[15].U16[4], 1, 1, 1, 1)
		VMACF_operation(5, state.v[27].U16[5], state.v[17].U16[5], state.v[15].U16[5], 1, 1, 1, 1)
		VMACF_operation(6, state.v[27].U16[6], state.v[17].U16[6], state.v[15].U16[6], 1, 1, 1, 1)
		VMACF_operation(7, state.v[27].U16[7], state.v[17].U16[7], state.v[15].U16[7], 1, 1, 1, 1)
	}


_04001DB0:	// 4001db0: <1e800007>	BGTZ      (R0>0) --> 1dd0
	sp_reg_pc = 0x04001DB0;
	if((_s32)state.r[S4] > 0)
	{
		{
			_u32    addr = (0x00000000 + state.r[S3]);
			int     shifter = ((addr & 0xf) << 3);

			if (shifter == 0 && (addr&3) == 0 )
			{
				addr &= 0xfff;
				*(_u32 *)&pDMEM[addr+12] = state.v[29].U32[0];
				*(_u32 *)&pDMEM[addr+8 ] = state.v[29].U32[1];
				*(_u32 *)&pDMEM[addr+4 ] = state.v[29].U32[2];
				*(_u32 *)&pDMEM[addr   ] = state.v[29].U32[3];
			}
			else
			{
				_u64    value1 = Load64_DMEM(addr+8);
				_u64    value2 = Load64_DMEM(addr);
				_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
				_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

				if (shifter > 0x40)
				{
					temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
					temp1 = 0;
				} else {
					temp1 = ((temp1 >> shifter) << shifter);
				}
				value1 = value1 & ~temp1;
				value2 = value2 & ~temp2;

				value1 |= (state.v[29].U64[0] & temp1);
				value2 |= (state.v[29].U64[1] & temp2);

				Save64_DMEM(value1, addr+8);
				Save64_DMEM(value2, addr  );
			}
		}
		goto _04001DD0;
	}


_04001DB4:	// 4001db4: <ea7d2000>	SQV       [S3 + 0x00] = vec29 <00>
	{
		_u32    addr = (0x00000000 + state.r[S3]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[29].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[29].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[29].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[29].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[29].U64[0] & temp1);
			value2 |= (state.v[29].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001DB8:	// 4001db8: <4b7894a3>	VGE       vec18 = (vec18 >= vec24[3])
	rsp_cop2_vge_element(&state.v[18], &state.v[18], &state.v[24].U16[4]);


_04001DBC:	// 4001dbc: <4b58ad54>	VADDC	vec21 = vec21 + vec24[2]
	{
		_u16		flag0 = 0;
		_u16		s2value = state.v[24].U16[5];
		VADDC_operation(0, state.v[21].U16[0], state.v[21].U16[0], s2value, 1, 0, 0, 1)
		VADDC_operation(1, state.v[21].U16[1], state.v[21].U16[1], s2value, 1, 0, 0, 1)
		VADDC_operation(2, state.v[21].U16[2], state.v[21].U16[2], s2value, 1, 0, 0, 1)
		VADDC_operation(3, state.v[21].U16[3], state.v[21].U16[3], s2value, 1, 0, 0, 1)
		VADDC_operation(4, state.v[21].U16[4], state.v[21].U16[4], s2value, 1, 0, 0, 1)
		VADDC_operation(5, state.v[21].U16[5], state.v[21].U16[5], s2value, 1, 0, 0, 1)
		VADDC_operation(6, state.v[21].U16[6], state.v[21].U16[6], s2value, 1, 0, 0, 1)
		VADDC_operation(7, state.v[21].U16[7], state.v[21].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = flag0;
	}


_04001DC0:	// 4001dc0: <ea3b2000>	SQV       [S1 + 0x00] = vec27 <00>
	{
		_u32    addr = (0x00000000 + state.r[S1]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[27].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[27].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[27].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[27].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[27].U64[0] & temp1);
			value2 |= (state.v[27].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001DC4:	// 4001dc4: <4b38a510>	VADD      vec20 = vec20 + vec24[1]
	{
		_u16		flag0 = state.flag[0];
		_u16		s2value = state.v[24].U16[6];
		VADD_operation(0, state.v[20].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VADD_operation(1, state.v[20].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VADD_operation(2, state.v[20].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VADD_operation(3, state.v[20].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VADD_operation(4, state.v[20].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VADD_operation(5, state.v[20].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VADD_operation(6, state.v[20].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VADD_operation(7, state.v[20].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


_04001DC8:	// 4001dc8: <09000778>	J         04001de0
	goto _04001DE0;


_04001DCC:	// 4001dcc: <00000000>	NOP       


_04001DD0:	// 4001dd0: <4b7894a4>	VCL ?-?
	rsp_cop2_vcl_element(&state.v[18], &state.v[18], &state.v[24].U16[4]);


_04001DD4:	// 4001dd4: <4b58ad54>	VADDC	vec21 = vec21 + vec24[2]
	{
		_u16		flag0 = 0;
		_u16		s2value = state.v[24].U16[5];
		VADDC_operation(0, state.v[21].U16[0], state.v[21].U16[0], s2value, 1, 0, 0, 1)
		VADDC_operation(1, state.v[21].U16[1], state.v[21].U16[1], s2value, 1, 0, 0, 1)
		VADDC_operation(2, state.v[21].U16[2], state.v[21].U16[2], s2value, 1, 0, 0, 1)
		VADDC_operation(3, state.v[21].U16[3], state.v[21].U16[3], s2value, 1, 0, 0, 1)
		VADDC_operation(4, state.v[21].U16[4], state.v[21].U16[4], s2value, 1, 0, 0, 1)
		VADDC_operation(5, state.v[21].U16[5], state.v[21].U16[5], s2value, 1, 0, 0, 1)
		VADDC_operation(6, state.v[21].U16[6], state.v[21].U16[6], s2value, 1, 0, 0, 1)
		VADDC_operation(7, state.v[21].U16[7], state.v[21].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = flag0;
	}


_04001DD8:	// 4001dd8: <ea3b2000>	SQV       [S1 + 0x00] = vec27 <00>
	{
		_u32    addr = (0x00000000 + state.r[S1]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[27].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[27].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[27].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[27].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[27].U64[0] & temp1);
			value2 |= (state.v[27].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001DDC:	// 4001ddc: <4b38a510>	VADD      vec20 = vec20 + vec24[1]
	{
		_u16		flag0 = state.flag[0];
		_u16		s2value = state.v[24].U16[6];
		VADD_operation(0, state.v[20].U16[0], state.v[20].U16[0], s2value, 1, 0, 0, 1)
		VADD_operation(1, state.v[20].U16[1], state.v[20].U16[1], s2value, 1, 0, 0, 1)
		VADD_operation(2, state.v[20].U16[2], state.v[20].U16[2], s2value, 1, 0, 0, 1)
		VADD_operation(3, state.v[20].U16[3], state.v[20].U16[3], s2value, 1, 0, 0, 1)
		VADD_operation(4, state.v[20].U16[4], state.v[20].U16[4], s2value, 1, 0, 0, 1)
		VADD_operation(5, state.v[20].U16[5], state.v[20].U16[5], s2value, 1, 0, 0, 1)
		VADD_operation(6, state.v[20].U16[6], state.v[20].U16[6], s2value, 1, 0, 0, 1)
		VADD_operation(7, state.v[20].U16[7], state.v[20].U16[7], s2value, 1, 0, 0, 1)
		state.flag[0] = 0x0000;
	}


_04001DE0:	// 4001de0: <4bd89400>	VMULF     vec16 = ( acc = (vec18 * vec24[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[1];
		VMULF_operation(0, state.v[16].U16[0], state.v[18].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[16].U16[1], state.v[18].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[16].U16[2], state.v[18].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[16].U16[3], state.v[18].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[16].U16[4], state.v[18].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[16].U16[5], state.v[18].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[16].U16[6], state.v[18].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[16].U16[7], state.v[18].U16[7], s2value, 1, 0, 0, 1)
	}


_04001DE4:	// 4001de4: <21cefff0>	ADDI      T6 = T6 + fff0
	state.r[T6] = state.r[T6] + 0xFFFFFFF0;


_04001DE8:	// 4001de8: <4bf893c0>	VMULF     vec15 = ( acc = (vec18 * vec24[7]) << 1 ) >> 16
	{
		_u16		s2value = state.v[24].U16[0];
		VMULF_operation(0, state.v[15].U16[0], state.v[18].U16[0], s2value, 1, 0, 0, 1)
		VMULF_operation(1, state.v[15].U16[1], state.v[18].U16[1], s2value, 1, 0, 0, 1)
		VMULF_operation(2, state.v[15].U16[2], state.v[18].U16[2], s2value, 1, 0, 0, 1)
		VMULF_operation(3, state.v[15].U16[3], state.v[18].U16[3], s2value, 1, 0, 0, 1)
		VMULF_operation(4, state.v[15].U16[4], state.v[18].U16[4], s2value, 1, 0, 0, 1)
		VMULF_operation(5, state.v[15].U16[5], state.v[18].U16[5], s2value, 1, 0, 0, 1)
		VMULF_operation(6, state.v[15].U16[6], state.v[18].U16[6], s2value, 1, 0, 0, 1)
		VMULF_operation(7, state.v[15].U16[7], state.v[18].U16[7], s2value, 1, 0, 0, 1)
	}


_04001DEC:	// 4001dec: <22730010>	ADDI      S3 = S3 + 0010
	state.r[S3] = state.r[S3] + 0x0010;


_04001DF0:	// 4001df0: <4bcae700>	VMULF     vec28 = ( acc = (vec28 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[28].U16[0], state.v[28].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[28].U16[1], state.v[28].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[28].U16[2], state.v[28].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[28].U16[3], state.v[28].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[28].U16[4], state.v[28].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[28].U16[5], state.v[28].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[28].U16[6], state.v[28].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[28].U16[7], state.v[28].U16[7], s2value, 0, 1, 1, 1)
	}


_04001DF4:	// 4001df4: <022f8820>	ADD       S1 = S1+T7
	state.r[S1] = (state.r[S1] + state.r[T7]);


_04001DF8:	// 4001df8: <4a108f08>	VMACF     vec28 = ( acc += (vec17 * vec16[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[28].U16[0], state.v[17].U16[0], state.v[16].U16[0], 1, 0, 0, 1)
		VMACF_operation(1, state.v[28].U16[1], state.v[17].U16[1], state.v[16].U16[1], 1, 0, 0, 1)
		VMACF_operation(2, state.v[28].U16[2], state.v[17].U16[2], state.v[16].U16[2], 1, 0, 0, 1)
		VMACF_operation(3, state.v[28].U16[3], state.v[17].U16[3], state.v[16].U16[3], 1, 0, 0, 1)
		VMACF_operation(4, state.v[28].U16[4], state.v[17].U16[4], state.v[16].U16[4], 1, 0, 0, 1)
		VMACF_operation(5, state.v[28].U16[5], state.v[17].U16[5], state.v[16].U16[5], 1, 0, 0, 1)
		VMACF_operation(6, state.v[28].U16[6], state.v[17].U16[6], state.v[16].U16[6], 1, 0, 0, 1)
		VMACF_operation(7, state.v[28].U16[7], state.v[17].U16[7], state.v[16].U16[7], 1, 0, 0, 1)
	}


_04001DFC:	// 4001dfc: <21ad0010>	ADDI      T5 = T5 + 0010
	state.r[T5] = state.r[T5] + 0x0010;


_04001E00:	// 4001e00: <4bcad680>	VMULF     vec26 = ( acc = (vec26 * vec10[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[10].U16[1];
		VMULF_operation(0, state.v[26].U16[0], state.v[26].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[26].U16[1], state.v[26].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[26].U16[2], state.v[26].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[26].U16[3], state.v[26].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[26].U16[4], state.v[26].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[26].U16[5], state.v[26].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[26].U16[6], state.v[26].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[26].U16[7], state.v[26].U16[7], s2value, 0, 1, 1, 1)
	}


_04001E04:	// 4001e04: <4a0f8e88>	VMACF     vec26 = ( acc += (vec17 * vec15[<none>]) << 1 ) >> 16
	{
		VMACF_operation(0, state.v[26].U16[0], state.v[17].U16[0], state.v[15].U16[0], 1, 1, 1, 1)
		VMACF_operation(1, state.v[26].U16[1], state.v[17].U16[1], state.v[15].U16[1], 1, 1, 1, 1)
		VMACF_operation(2, state.v[26].U16[2], state.v[17].U16[2], state.v[15].U16[2], 1, 1, 1, 1)
		VMACF_operation(3, state.v[26].U16[3], state.v[17].U16[3], state.v[15].U16[3], 1, 1, 1, 1)
		VMACF_operation(4, state.v[26].U16[4], state.v[17].U16[4], state.v[15].U16[4], 1, 1, 1, 1)
		VMACF_operation(5, state.v[26].U16[5], state.v[17].U16[5], state.v[15].U16[5], 1, 1, 1, 1)
		VMACF_operation(6, state.v[26].U16[6], state.v[17].U16[6], state.v[15].U16[6], 1, 1, 1, 1)
		VMACF_operation(7, state.v[26].U16[7], state.v[17].U16[7], state.v[15].U16[7], 1, 1, 1, 1)
	}


_04001E08:	// 4001e08: <ea5c2000>	SQV       [S2 + 0x00] = vec28 <00>
	{
		_u32    addr = (0x00000000 + state.r[S2]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[28].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[28].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[28].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[28].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[28].U64[0] & temp1);
			value2 |= (state.v[28].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001E0C:	// 4001e0c: <22520010>	ADDI      S2 = S2 + 0010
	state.r[S2] = state.r[S2] + 0x0010;

_04001E10:
	;
}

void DKR1E3C_1F30(void)
{

_04001E3C:	// 4001e3c: <c81f2000>	LQV       vec31 <00> = [R0 + 0x00]
	{
		_u32 addr = (0x00000000 + 0);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[31].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[31].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[31].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[31].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[31].U64[0] = state.v[31].U64[0] & ~temp1;
			state.v[31].U64[1] = state.v[31].U64[1] & ~temp2;
			state.v[31].U64[0] = state.v[31].U64[0] | value1;
			state.v[31].U64[1] = state.v[31].U64[1] | value2;
		}
	}


_04001E40:	// 4001e40: <97120004>	LHU       S2 = [T8+0004]
	state.r[S2] = (_s32)(_u16)Load16_DMEM((state.r[T8] + 0x00000004) & 0xfff);


_04001E44:	// 4001e44: <1240003b>	BEQ       (R0==S2) --> 1f34
	sp_reg_pc = 0x04001E44;
	if (state.r[S2] == 0)
	{
		goto _04001F34;
	}


_04001E48:	// 4001e48: <00000000>	NOP       


_04001E4C:	// 4001e4c: <3322ffff>	ANDI      V0 = T9 & ffff
	state.r[V0] = (state.r[T9] & 0x0000FFFF);


_04001E50:	// 4001e50: <204205c0>	ADDI      V0 = V0 + 05c0
	state.r[V0] = state.r[V0] + 0x05C0;


_04001E54:	// 4001e54: <00190c02>	SRL       AT = T9 >> 16
	state.r[AT] = ((_u32)state.r[T9] >> 16);


_04001E58:	// 4001e58: <202105c0>	ADDI      AT = AT + 05c0
	state.r[AT] = state.r[AT] + 0x05C0;


_04001E5C:	// 4001e5c: <3351ffff>	ANDI      S1 = K0 & ffff
	state.r[S1] = (state.r[K0] & 0x0000FFFF);


_04001E60:	// 4001e60: <4891f000>	MTC2      vec30 <00> = S1
	state.v[30].U16[7] = (_u16)state.r[S1];


_04001E64:	// 4001e64: <12c00005>	BEQ       (R0==S6) --> 1e7c
	sp_reg_pc = 0x04001E64;
	if (state.r[S6] == 0)
	{
		goto _04001E7C;
	}


_04001E68:	// 4001e68: <00000000>	NOP       


_04001E6C:	// 4001e6c: <40033000>	MFC0      A2 = SP write DMA length
	state.r[V1] = 0;


_04001E70:	// 4001e70: <1460fffe>	BNE       (R0!=V1) --> 1e6c
	sp_reg_pc = 0x04001E70;
	if (state.r[V1] != 0)
	{
		goto _04001E6C;
	}


_04001E74:	// 4001e74: <00000000>	NOP       


_04001E78:	// 4001e78: <0000b020>	ADD       S6 = R0+R0
	state.r[S6] = (0 + 0);


_04001E7C:	// 4001e7c: <c8592000>	LQV       vec25 <00> = [V0 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[25].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[25].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[25].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[25].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[25].U64[0] = state.v[25].U64[0] & ~temp1;
			state.v[25].U64[1] = state.v[25].U64[1] & ~temp2;
			state.v[25].U64[0] = state.v[25].U64[0] | value1;
			state.v[25].U64[1] = state.v[25].U64[1] | value2;
		}
	}


_04001E80:	// 4001e80: <c83d2000>	LQV       vec29 <00> = [AT + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[29].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[29].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[29].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[29].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[29].U64[0] = state.v[29].U64[0] & ~temp1;
			state.v[29].U64[1] = state.v[29].U64[1] & ~temp2;
			state.v[29].U64[0] = state.v[29].U64[0] | value1;
			state.v[29].U64[1] = state.v[29].U64[1] | value2;
		}
	}


_04001E84:	// 4001e84: <c8582001>	LQV       vec24 <00> = [V0 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
			state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
			state.v[24].U64[0] = state.v[24].U64[0] | value1;
			state.v[24].U64[1] = state.v[24].U64[1] | value2;
		}
	}


_04001E88:	// 4001e88: <c83c2001>	LQV       vec28 <00> = [AT + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[28].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[28].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[28].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[28].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[28].U64[0] = state.v[28].U64[0] & ~temp1;
			state.v[28].U64[1] = state.v[28].U64[1] & ~temp2;
			state.v[28].U64[0] = state.v[28].U64[0] | value1;
			state.v[28].U64[1] = state.v[28].U64[1] | value2;
		}
	}


_04001E8C:	// 4001e8c: <4bdfce40>	VMULF     vec25 = ( acc = (vec25 * vec31[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[31].U16[1];
		VMULF_operation(0, state.v[25].U16[0], state.v[25].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[25].U16[1], state.v[25].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[25].U16[2], state.v[25].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[25].U16[3], state.v[25].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[25].U16[4], state.v[25].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[25].U16[5], state.v[25].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[25].U16[6], state.v[25].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[25].U16[7], state.v[25].U16[7], s2value, 0, 1, 1, 1)
	}


_04001E90:	// 4001e90: <c83b2002>	LQV       vec27 <00> = [AT + 0x20]
	{
		_u32 addr = (0x00000020 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}


_04001E94:	// 4001e94: <c8572002>	LQV       vec23 <00> = [V0 + 0x20]
	{
		_u32 addr = (0x00000020 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[23].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[23].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[23].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[23].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[23].U64[0] = state.v[23].U64[0] & ~temp1;
			state.v[23].U64[1] = state.v[23].U64[1] & ~temp2;
			state.v[23].U64[0] = state.v[23].U64[0] | value1;
			state.v[23].U64[1] = state.v[23].U64[1] | value2;
		}
	}


_04001E98:	// 4001e98: <4b1eee48>	VMACF     vec25 = ( acc += (vec29 * vec30[0]) << 1 ) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMACF_operation(0, state.v[25].U16[0], state.v[29].U16[0], s2value, 1, 0, 0, 1)
		VMACF_operation(1, state.v[25].U16[1], state.v[29].U16[1], s2value, 1, 0, 0, 1)
		VMACF_operation(2, state.v[25].U16[2], state.v[29].U16[2], s2value, 1, 0, 0, 1)
		VMACF_operation(3, state.v[25].U16[3], state.v[29].U16[3], s2value, 1, 0, 0, 1)
		VMACF_operation(4, state.v[25].U16[4], state.v[29].U16[4], s2value, 1, 0, 0, 1)
		VMACF_operation(5, state.v[25].U16[5], state.v[29].U16[5], s2value, 1, 0, 0, 1)
		VMACF_operation(6, state.v[25].U16[6], state.v[29].U16[6], s2value, 1, 0, 0, 1)
		VMACF_operation(7, state.v[25].U16[7], state.v[29].U16[7], s2value, 1, 0, 0, 1)
	}


_04001E9C:	// 4001e9c: <2252ffe0>	ADDI      S2 = S2 + ffe0
	state.r[S2] = state.r[S2] + 0xFFFFFFE0;


_04001EA0:	// 4001ea0: <4bdfc600>	VMULF     vec24 = ( acc = (vec24 * vec31[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[31].U16[1];
		VMULF_operation(0, state.v[24].U16[0], state.v[24].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[24].U16[1], state.v[24].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[24].U16[2], state.v[24].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[24].U16[3], state.v[24].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[24].U16[4], state.v[24].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[24].U16[5], state.v[24].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[24].U16[6], state.v[24].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[24].U16[7], state.v[24].U16[7], s2value, 0, 1, 1, 1)
	}


_04001EA4:	// 4001ea4: <c83a2003>	LQV       vec26 <00> = [AT + 0x30]
	{
		_u32 addr = (0x00000030 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[26].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[26].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[26].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[26].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[26].U64[0] = state.v[26].U64[0] & ~temp1;
			state.v[26].U64[1] = state.v[26].U64[1] & ~temp2;
			state.v[26].U64[0] = state.v[26].U64[0] | value1;
			state.v[26].U64[1] = state.v[26].U64[1] | value2;
		}
	}


_04001EA8:	// 4001ea8: <c8562003>	LQV       vec22 <00> = [V0 + 0x30]
	{
		_u32 addr = (0x00000030 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[22].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[22].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[22].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[22].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[22].U64[0] = state.v[22].U64[0] & ~temp1;
			state.v[22].U64[1] = state.v[22].U64[1] & ~temp2;
			state.v[22].U64[0] = state.v[22].U64[0] | value1;
			state.v[22].U64[1] = state.v[22].U64[1] | value2;
		}
	}


_04001EAC:	// 4001eac: <20210040>	ADDI      AT = AT + 0040
	state.r[AT] = state.r[AT] + 0x0040;


_04001EB0:	// 4001eb0: <20420040>	ADDI      V0 = V0 + 0040
	state.r[V0] = state.r[V0] + 0x0040;


_04001EB4:	// 4001eb4: <4b1ee608>	VMACF     vec24 = ( acc += (vec28 * vec30[0]) << 1 ) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMACF_operation(0, state.v[24].U16[0], state.v[28].U16[0], s2value, 1, 1, 1, 1)
		VMACF_operation(1, state.v[24].U16[1], state.v[28].U16[1], s2value, 1, 1, 1, 1)
		VMACF_operation(2, state.v[24].U16[2], state.v[28].U16[2], s2value, 1, 1, 1, 1)
		VMACF_operation(3, state.v[24].U16[3], state.v[28].U16[3], s2value, 1, 1, 1, 1)
		VMACF_operation(4, state.v[24].U16[4], state.v[28].U16[4], s2value, 1, 1, 1, 1)
		VMACF_operation(5, state.v[24].U16[5], state.v[28].U16[5], s2value, 1, 1, 1, 1)
		VMACF_operation(6, state.v[24].U16[6], state.v[28].U16[6], s2value, 1, 1, 1, 1)
		VMACF_operation(7, state.v[24].U16[7], state.v[28].U16[7], s2value, 1, 1, 1, 1)
	}


_04001EB8:	// 4001eb8: <1a40001c>	BLEZ      (R0<=0) --> 1f2c
	sp_reg_pc = 0x04001EB8;
	if ((_s32)state.r[S2] <= 0)
	{
		goto _04001F2C;
	}


_04001EBC:	// 4001ebc: <00000000>	NOP       


_04001EC0:	// 4001ec0: <4bdfbdc0>	VMULF     vec23 = ( acc = (vec23 * vec31[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[31].U16[1];
		VMULF_operation(0, state.v[23].U16[0], state.v[23].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[23].U16[1], state.v[23].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[23].U16[2], state.v[23].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[23].U16[3], state.v[23].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[23].U16[4], state.v[23].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[23].U16[5], state.v[23].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[23].U16[6], state.v[23].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[23].U16[7], state.v[23].U16[7], s2value, 0, 1, 1, 1)
	}


_04001EC4:	// 4001ec4: <e859207c>	SQV       [V0 + 0xc0] = vec25 <00>
	{
		_u32    addr = (0xFFFFFFC0 + state.r[V0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[25].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[25].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[25].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[25].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[25].U64[0] & temp1);
			value2 |= (state.v[25].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001EC8:	// 4001ec8: <c83d2000>	LQV       vec29 <00> = [AT + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[29].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[29].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[29].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[29].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[29].U64[0] = state.v[29].U64[0] & ~temp1;
			state.v[29].U64[1] = state.v[29].U64[1] & ~temp2;
			state.v[29].U64[0] = state.v[29].U64[0] | value1;
			state.v[29].U64[1] = state.v[29].U64[1] | value2;
		}
	}


_04001ECC:	// 4001ecc: <c8592000>	LQV       vec25 <00> = [V0 + 0x00]
	{
		_u32 addr = (0x00000000 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[25].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[25].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[25].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[25].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[25].U64[0] = state.v[25].U64[0] & ~temp1;
			state.v[25].U64[1] = state.v[25].U64[1] & ~temp2;
			state.v[25].U64[0] = state.v[25].U64[0] | value1;
			state.v[25].U64[1] = state.v[25].U64[1] | value2;
		}
	}


_04001ED0:	// 4001ed0: <4b1eddc8>	VMACF     vec23 = ( acc += (vec27 * vec30[0]) << 1 ) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMACF_operation(0, state.v[23].U16[0], state.v[27].U16[0], s2value, 1, 0, 0, 1)
		VMACF_operation(1, state.v[23].U16[1], state.v[27].U16[1], s2value, 1, 0, 0, 1)
		VMACF_operation(2, state.v[23].U16[2], state.v[27].U16[2], s2value, 1, 0, 0, 1)
		VMACF_operation(3, state.v[23].U16[3], state.v[27].U16[3], s2value, 1, 0, 0, 1)
		VMACF_operation(4, state.v[23].U16[4], state.v[27].U16[4], s2value, 1, 0, 0, 1)
		VMACF_operation(5, state.v[23].U16[5], state.v[27].U16[5], s2value, 1, 0, 0, 1)
		VMACF_operation(6, state.v[23].U16[6], state.v[27].U16[6], s2value, 1, 0, 0, 1)
		VMACF_operation(7, state.v[23].U16[7], state.v[27].U16[7], s2value, 1, 0, 0, 1)
	}


_04001ED4:	// 4001ed4: <4bdfb580>	VMULF     vec22 = ( acc = (vec22 * vec31[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[31].U16[1];
		VMULF_operation(0, state.v[22].U16[0], state.v[22].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[22].U16[1], state.v[22].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[22].U16[2], state.v[22].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[22].U16[3], state.v[22].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[22].U16[4], state.v[22].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[22].U16[5], state.v[22].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[22].U16[6], state.v[22].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[22].U16[7], state.v[22].U16[7], s2value, 0, 1, 1, 1)
	}


_04001ED8:	// 4001ed8: <e858207d>	SQV       [V0 + 0xd0] = vec24 <00>
	{
		_u32    addr = (0xFFFFFFD0 + state.r[V0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[24].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[24].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[24].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[24].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[24].U64[0] & temp1);
			value2 |= (state.v[24].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001EDC:	// 4001edc: <c83c2001>	LQV       vec28 <00> = [AT + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[28].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[28].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[28].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[28].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[28].U64[0] = state.v[28].U64[0] & ~temp1;
			state.v[28].U64[1] = state.v[28].U64[1] & ~temp2;
			state.v[28].U64[0] = state.v[28].U64[0] | value1;
			state.v[28].U64[1] = state.v[28].U64[1] | value2;
		}
	}


_04001EE0:	// 4001ee0: <c8582001>	LQV       vec24 <00> = [V0 + 0x10]
	{
		_u32 addr = (0x00000010 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[24].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[24].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[24].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[24].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[24].U64[0] = state.v[24].U64[0] & ~temp1;
			state.v[24].U64[1] = state.v[24].U64[1] & ~temp2;
			state.v[24].U64[0] = state.v[24].U64[0] | value1;
			state.v[24].U64[1] = state.v[24].U64[1] | value2;
		}
	}


_04001EE4:	// 4001ee4: <4b1ed588>	VMACF     vec22 = ( acc += (vec26 * vec30[0]) << 1 ) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMACF_operation(0, state.v[22].U16[0], state.v[26].U16[0], s2value, 1, 0, 0, 1)
		VMACF_operation(1, state.v[22].U16[1], state.v[26].U16[1], s2value, 1, 0, 0, 1)
		VMACF_operation(2, state.v[22].U16[2], state.v[26].U16[2], s2value, 1, 0, 0, 1)
		VMACF_operation(3, state.v[22].U16[3], state.v[26].U16[3], s2value, 1, 0, 0, 1)
		VMACF_operation(4, state.v[22].U16[4], state.v[26].U16[4], s2value, 1, 0, 0, 1)
		VMACF_operation(5, state.v[22].U16[5], state.v[26].U16[5], s2value, 1, 0, 0, 1)
		VMACF_operation(6, state.v[22].U16[6], state.v[26].U16[6], s2value, 1, 0, 0, 1)
		VMACF_operation(7, state.v[22].U16[7], state.v[26].U16[7], s2value, 1, 0, 0, 1)
	}


_04001EE8:	// 4001ee8: <20210040>	ADDI      AT = AT + 0040
	state.r[AT] = state.r[AT] + 0x0040;


_04001EEC:	// 4001eec: <4bdfce40>	VMULF     vec25 = ( acc = (vec25 * vec31[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[31].U16[1];
		VMULF_operation(0, state.v[25].U16[0], state.v[25].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[25].U16[1], state.v[25].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[25].U16[2], state.v[25].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[25].U16[3], state.v[25].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[25].U16[4], state.v[25].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[25].U16[5], state.v[25].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[25].U16[6], state.v[25].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[25].U16[7], state.v[25].U16[7], s2value, 0, 1, 1, 1)
	}


_04001EF0:	// 4001ef0: <e857207e>	SQV       [V0 + 0xe0] = vec23 <00>
	{
		_u32    addr = (0xFFFFFFE0 + state.r[V0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[23].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[23].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[23].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[23].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[23].U64[0] & temp1);
			value2 |= (state.v[23].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001EF4:	// 4001ef4: <c83b207e>	LQV       vec27 <00> = [AT + 0xe0]
	{
		_u32 addr = (0xFFFFFFE0 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[27].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[27].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[27].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[27].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[27].U64[0] = state.v[27].U64[0] & ~temp1;
			state.v[27].U64[1] = state.v[27].U64[1] & ~temp2;
			state.v[27].U64[0] = state.v[27].U64[0] | value1;
			state.v[27].U64[1] = state.v[27].U64[1] | value2;
		}
	}


_04001EF8:	// 4001ef8: <c8572002>	LQV       vec23 <00> = [V0 + 0x20]
	{
		_u32 addr = (0x00000020 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[23].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[23].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[23].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[23].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[23].U64[0] = state.v[23].U64[0] & ~temp1;
			state.v[23].U64[1] = state.v[23].U64[1] & ~temp2;
			state.v[23].U64[0] = state.v[23].U64[0] | value1;
			state.v[23].U64[1] = state.v[23].U64[1] | value2;
		}
	}


_04001EFC:	// 4001efc: <4b1eee48>	VMACF     vec25 = ( acc += (vec29 * vec30[0]) << 1 ) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMACF_operation(0, state.v[25].U16[0], state.v[29].U16[0], s2value, 1, 0, 0, 1)
		VMACF_operation(1, state.v[25].U16[1], state.v[29].U16[1], s2value, 1, 0, 0, 1)
		VMACF_operation(2, state.v[25].U16[2], state.v[29].U16[2], s2value, 1, 0, 0, 1)
		VMACF_operation(3, state.v[25].U16[3], state.v[29].U16[3], s2value, 1, 0, 0, 1)
		VMACF_operation(4, state.v[25].U16[4], state.v[29].U16[4], s2value, 1, 0, 0, 1)
		VMACF_operation(5, state.v[25].U16[5], state.v[29].U16[5], s2value, 1, 0, 0, 1)
		VMACF_operation(6, state.v[25].U16[6], state.v[29].U16[6], s2value, 1, 0, 0, 1)
		VMACF_operation(7, state.v[25].U16[7], state.v[29].U16[7], s2value, 1, 0, 0, 1)
	}


_04001F00:	// 4001f00: <2252ffc0>	ADDI      S2 = S2 + ffc0
	state.r[S2] = state.r[S2] + 0xFFFFFFC0;


_04001F04:	// 4001f04: <4bdfc600>	VMULF     vec24 = ( acc = (vec24 * vec31[6]) << 1 ) >> 16
	{
		_u16		s2value = state.v[31].U16[1];
		VMULF_operation(0, state.v[24].U16[0], state.v[24].U16[0], s2value, 0, 1, 1, 1)
		VMULF_operation(1, state.v[24].U16[1], state.v[24].U16[1], s2value, 0, 1, 1, 1)
		VMULF_operation(2, state.v[24].U16[2], state.v[24].U16[2], s2value, 0, 1, 1, 1)
		VMULF_operation(3, state.v[24].U16[3], state.v[24].U16[3], s2value, 0, 1, 1, 1)
		VMULF_operation(4, state.v[24].U16[4], state.v[24].U16[4], s2value, 0, 1, 1, 1)
		VMULF_operation(5, state.v[24].U16[5], state.v[24].U16[5], s2value, 0, 1, 1, 1)
		VMULF_operation(6, state.v[24].U16[6], state.v[24].U16[6], s2value, 0, 1, 1, 1)
		VMULF_operation(7, state.v[24].U16[7], state.v[24].U16[7], s2value, 0, 1, 1, 1)
	}


_04001F08:	// 4001f08: <e856207f>	SQV       [V0 + 0xf0] = vec22 <00>
	{
		_u32    addr = (0xFFFFFFF0 + state.r[V0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[22].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[22].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[22].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[22].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[22].U64[0] & temp1);
			value2 |= (state.v[22].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001F0C:	// 4001f0c: <c83a207f>	LQV       vec26 <00> = [AT + 0xf0]
	{
		_u32 addr = (0xFFFFFFF0 + state.r[AT]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[26].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[26].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[26].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[26].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[26].U64[0] = state.v[26].U64[0] & ~temp1;
			state.v[26].U64[1] = state.v[26].U64[1] & ~temp2;
			state.v[26].U64[0] = state.v[26].U64[0] | value1;
			state.v[26].U64[1] = state.v[26].U64[1] | value2;
		}
	}


_04001F10:	// 4001f10: <c8562003>	LQV       vec22 <00> = [V0 + 0x30]
	{
		_u32 addr = (0x00000030 + state.r[V0]);
		int shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			state.v[22].U32[0] = *(_u32 *)&pDMEM[addr+12];
			state.v[22].U32[1] = *(_u32 *)&pDMEM[addr+8];
			state.v[22].U32[2] = *(_u32 *)&pDMEM[addr+4];
			state.v[22].U32[3] = *(_u32 *)&pDMEM[addr];
		}
		else
		{
			_u64		temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64		temp2 = 0xFFFFFFFFFFFFFFFF;
			_u64		value1 = Load64_DMEM(addr+8);
			_u64		value2 = Load64_DMEM(addr);
			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & temp1;
			value2 = value2 & temp2;

			state.v[22].U64[0] = state.v[22].U64[0] & ~temp1;
			state.v[22].U64[1] = state.v[22].U64[1] & ~temp2;
			state.v[22].U64[0] = state.v[22].U64[0] | value1;
			state.v[22].U64[1] = state.v[22].U64[1] | value2;
		}
	}


_04001F14:	// 4001f14: <4b1ee608>	VMACF     vec24 = ( acc += (vec28 * vec30[0]) << 1 ) >> 16
	{
		_u16		s2value = state.v[30].U16[7];
		VMACF_operation(0, state.v[24].U16[0], state.v[28].U16[0], s2value, 1, 1, 1, 1)
		VMACF_operation(1, state.v[24].U16[1], state.v[28].U16[1], s2value, 1, 1, 1, 1)
		VMACF_operation(2, state.v[24].U16[2], state.v[28].U16[2], s2value, 1, 1, 1, 1)
		VMACF_operation(3, state.v[24].U16[3], state.v[28].U16[3], s2value, 1, 1, 1, 1)
		VMACF_operation(4, state.v[24].U16[4], state.v[28].U16[4], s2value, 1, 1, 1, 1)
		VMACF_operation(5, state.v[24].U16[5], state.v[28].U16[5], s2value, 1, 1, 1, 1)
		VMACF_operation(6, state.v[24].U16[6], state.v[28].U16[6], s2value, 1, 1, 1, 1)
		VMACF_operation(7, state.v[24].U16[7], state.v[28].U16[7], s2value, 1, 1, 1, 1)
	}


_04001F18:	// 4001f18: <1e40ffe9>	BGTZ      (R0>0) --> 1ec0
	sp_reg_pc = 0x04001F18;
	if((_s32)state.r[S2] > 0)
	{
		state.r[V0] = state.r[V0] + 0x0040;
		goto _04001EC0;
	}


_04001F1C:	// 4001f1c: <20420040>	ADDI      V0 = V0 + 0040
	state.r[V0] = state.r[V0] + 0x0040;


_04001F20:	// 4001f20: <22520020>	ADDI      S2 = S2 + 0020
	state.r[S2] = state.r[S2] + 0x0020;


_04001F24:	// 4001f24: <1a400003>	BLEZ      (R0<=0) --> 1f34
	sp_reg_pc = 0x04001F24;
	if ((_s32)state.r[S2] <= 0)
	{
		goto _04001F34;
	}


_04001F28:	// 4001f28: <00000000>	NOP       


_04001F2C:	// 4001f2c: <e859207c>	SQV       [V0 + 0xc0] = vec25 <00>
	{
		_u32    addr = (0xFFFFFFC0 + state.r[V0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[25].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[25].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[25].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[25].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[25].U64[0] & temp1);
			value2 |= (state.v[25].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}


_04001F30:	// 4001f30: <e858207d>	SQV       [V0 + 0xd0] = vec24 <00>
	{
		_u32    addr = (0xFFFFFFD0 + state.r[V0]);
		int     shifter = ((addr & 0xf) << 3);

		if (shifter == 0 && (addr&3) == 0 )
		{
			addr &= 0xfff;
			*(_u32 *)&pDMEM[addr+12] = state.v[24].U32[0];
			*(_u32 *)&pDMEM[addr+8 ] = state.v[24].U32[1];
			*(_u32 *)&pDMEM[addr+4 ] = state.v[24].U32[2];
			*(_u32 *)&pDMEM[addr   ] = state.v[24].U32[3];
		}
		else
		{
			_u64    value1 = Load64_DMEM(addr+8);
			_u64    value2 = Load64_DMEM(addr);
			_u64    temp1 = 0xFFFFFFFFFFFFFFFF;
			_u64    temp2 = 0xFFFFFFFFFFFFFFFF;

			if (shifter > 0x40)
			{
				temp2 = ((temp2 >> (shifter-0x40)) << (shifter-0x40));
				temp1 = 0;
			} else {
				temp1 = ((temp1 >> shifter) << shifter);
			}
			value1 = value1 & ~temp1;
			value2 = value2 & ~temp2;

			value1 |= (state.v[24].U64[0] & temp1);
			value2 |= (state.v[24].U64[1] & temp2);

			Save64_DMEM(value1, addr+8);
			Save64_DMEM(value2, addr  );
		}
	}

_04001F34:
	;
}
